1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/io.h> 35 36 #if defined(CONFIG_HARD_I2C) 37 38 #include <asm/arch/clock.h> 39 #include <asm/arch/imx-regs.h> 40 41 struct mxc_i2c_regs { 42 uint32_t iadr; 43 uint32_t ifdr; 44 uint32_t i2cr; 45 uint32_t i2sr; 46 uint32_t i2dr; 47 }; 48 49 #define I2CR_IEN (1 << 7) 50 #define I2CR_IIEN (1 << 6) 51 #define I2CR_MSTA (1 << 5) 52 #define I2CR_MTX (1 << 4) 53 #define I2CR_TX_NO_AK (1 << 3) 54 #define I2CR_RSTA (1 << 2) 55 56 #define I2SR_ICF (1 << 7) 57 #define I2SR_IBB (1 << 5) 58 #define I2SR_IIF (1 << 1) 59 #define I2SR_RX_NO_AK (1 << 0) 60 61 #if defined(CONFIG_SYS_I2C_MX31_PORT1) 62 #define I2C_BASE 0x43f80000 63 #define I2C_CLK_OFFSET 26 64 #elif defined (CONFIG_SYS_I2C_MX31_PORT2) 65 #define I2C_BASE 0x43f98000 66 #define I2C_CLK_OFFSET 28 67 #elif defined (CONFIG_SYS_I2C_MX31_PORT3) 68 #define I2C_BASE 0x43f84000 69 #define I2C_CLK_OFFSET 30 70 #elif defined(CONFIG_SYS_I2C_MX53_PORT1) 71 #define I2C_BASE I2C1_BASE_ADDR 72 #elif defined(CONFIG_SYS_I2C_MX53_PORT2) 73 #define I2C_BASE I2C2_BASE_ADDR 74 #elif defined(CONFIG_SYS_I2C_MX35_PORT1) 75 #define I2C_BASE I2C_BASE_ADDR 76 #elif defined(CONFIG_SYS_I2C_MX35_PORT2) 77 #define I2C_BASE I2C2_BASE_ADDR 78 #elif defined(CONFIG_SYS_I2C_MX35_PORT3) 79 #define I2C_BASE I2C3_BASE_ADDR 80 #else 81 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" 82 #endif 83 84 #define I2C_MAX_TIMEOUT 10000 85 86 static u16 i2c_clk_div[50][2] = { 87 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 88 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 89 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 90 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 91 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 92 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 93 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 94 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 95 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 96 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 97 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 98 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 99 { 3072, 0x1E }, { 3840, 0x1F } 100 }; 101 102 static u8 clk_div; 103 104 /* 105 * Calculate and set proper clock divider 106 */ 107 static void i2c_imx_set_clk(unsigned int rate) 108 { 109 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 110 unsigned int i2c_clk_rate; 111 unsigned int div; 112 113 #if defined(CONFIG_MX31) 114 struct clock_control_regs *sc_regs = 115 (struct clock_control_regs *)CCM_BASE; 116 117 /* start the required I2C clock */ 118 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), 119 &sc_regs->cgr0); 120 #endif 121 122 /* Divider value calculation */ 123 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 124 div = (i2c_clk_rate + rate - 1) / rate; 125 if (div < i2c_clk_div[0][0]) 126 clk_div = 0; 127 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 128 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 129 else 130 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 131 ; 132 133 /* Store divider value */ 134 writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr); 135 } 136 137 /* 138 * Reset I2C Controller 139 */ 140 void i2c_reset(void) 141 { 142 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 143 144 writeb(0, &i2c_regs->i2cr); /* Reset module */ 145 writeb(0, &i2c_regs->i2sr); 146 } 147 148 /* 149 * Init I2C Bus 150 */ 151 void i2c_init(int speed, int unused) 152 { 153 i2c_imx_set_clk(speed); 154 i2c_reset(); 155 } 156 157 /* 158 * Set I2C Speed 159 */ 160 int i2c_set_bus_speed(unsigned int speed) 161 { 162 i2c_init(speed, 0); 163 return 0; 164 } 165 166 /* 167 * Get I2C Speed 168 */ 169 unsigned int i2c_get_bus_speed(void) 170 { 171 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; 172 } 173 174 /* 175 * Wait for bus to be busy (or free if for_busy = 0) 176 * 177 * for_busy = 1: Wait for IBB to be asserted 178 * for_busy = 0: Wait for IBB to be de-asserted 179 */ 180 int i2c_imx_bus_busy(int for_busy) 181 { 182 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 183 unsigned int temp; 184 185 int timeout = I2C_MAX_TIMEOUT; 186 187 while (timeout--) { 188 temp = readb(&i2c_regs->i2sr); 189 190 if (for_busy && (temp & I2SR_IBB)) 191 return 0; 192 if (!for_busy && !(temp & I2SR_IBB)) 193 return 0; 194 195 udelay(1); 196 } 197 198 return 1; 199 } 200 201 /* 202 * Wait for transaction to complete 203 */ 204 int i2c_imx_trx_complete(void) 205 { 206 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 207 int timeout = I2C_MAX_TIMEOUT; 208 209 while (timeout--) { 210 if (readb(&i2c_regs->i2sr) & I2SR_IIF) { 211 writeb(0, &i2c_regs->i2sr); 212 return 0; 213 } 214 215 udelay(1); 216 } 217 218 return 1; 219 } 220 221 /* 222 * Check if the transaction was ACKed 223 */ 224 int i2c_imx_acked(void) 225 { 226 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 227 228 return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK; 229 } 230 231 /* 232 * Start the controller 233 */ 234 int i2c_imx_start(void) 235 { 236 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 237 unsigned int temp = 0; 238 int result; 239 240 writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr); 241 242 /* Enable I2C controller */ 243 writeb(0, &i2c_regs->i2sr); 244 writeb(I2CR_IEN, &i2c_regs->i2cr); 245 246 /* Wait controller to be stable */ 247 udelay(50); 248 249 /* Start I2C transaction */ 250 temp = readb(&i2c_regs->i2cr); 251 temp |= I2CR_MSTA; 252 writeb(temp, &i2c_regs->i2cr); 253 254 result = i2c_imx_bus_busy(1); 255 if (result) 256 return result; 257 258 temp |= I2CR_MTX | I2CR_TX_NO_AK; 259 writeb(temp, &i2c_regs->i2cr); 260 261 return 0; 262 } 263 264 /* 265 * Stop the controller 266 */ 267 void i2c_imx_stop(void) 268 { 269 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 270 unsigned int temp = 0; 271 272 /* Stop I2C transaction */ 273 temp = readb(&i2c_regs->i2cr); 274 temp |= ~(I2CR_MSTA | I2CR_MTX); 275 writeb(temp, &i2c_regs->i2cr); 276 277 i2c_imx_bus_busy(0); 278 279 /* Disable I2C controller */ 280 writeb(0, &i2c_regs->i2cr); 281 } 282 283 /* 284 * Set chip address and access mode 285 * 286 * read = 1: READ access 287 * read = 0: WRITE access 288 */ 289 int i2c_imx_set_chip_addr(uchar chip, int read) 290 { 291 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 292 int ret; 293 294 writeb((chip << 1) | read, &i2c_regs->i2dr); 295 296 ret = i2c_imx_trx_complete(); 297 if (ret) 298 return ret; 299 300 ret = i2c_imx_acked(); 301 if (ret) 302 return ret; 303 304 return ret; 305 } 306 307 /* 308 * Write register address 309 */ 310 int i2c_imx_set_reg_addr(uint addr, int alen) 311 { 312 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 313 int ret; 314 int i; 315 316 for (i = 0; i < (8 * alen); i += 8) { 317 writeb((addr >> i) & 0xff, &i2c_regs->i2dr); 318 319 ret = i2c_imx_trx_complete(); 320 if (ret) 321 break; 322 323 ret = i2c_imx_acked(); 324 if (ret) 325 break; 326 } 327 328 return ret; 329 } 330 331 /* 332 * Try if a chip add given address responds (probe the chip) 333 */ 334 int i2c_probe(uchar chip) 335 { 336 int ret; 337 338 ret = i2c_imx_start(); 339 if (ret) 340 return ret; 341 342 ret = i2c_imx_set_chip_addr(chip, 0); 343 if (ret) 344 return ret; 345 346 i2c_imx_stop(); 347 348 return ret; 349 } 350 351 /* 352 * Read data from I2C device 353 */ 354 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 355 { 356 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 357 int ret; 358 unsigned int temp; 359 int i; 360 361 ret = i2c_imx_start(); 362 if (ret) 363 return ret; 364 365 /* write slave address */ 366 ret = i2c_imx_set_chip_addr(chip, 0); 367 if (ret) 368 return ret; 369 370 ret = i2c_imx_set_reg_addr(addr, alen); 371 if (ret) 372 return ret; 373 374 temp = readb(&i2c_regs->i2cr); 375 temp |= I2CR_RSTA; 376 writeb(temp, &i2c_regs->i2cr); 377 378 ret = i2c_imx_set_chip_addr(chip, 1); 379 if (ret) 380 return ret; 381 382 /* setup bus to read data */ 383 temp = readb(&i2c_regs->i2cr); 384 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 385 if (len == 1) 386 temp |= I2CR_TX_NO_AK; 387 writeb(temp, &i2c_regs->i2cr); 388 readb(&i2c_regs->i2dr); 389 390 /* read data */ 391 for (i = 0; i < len; i++) { 392 ret = i2c_imx_trx_complete(); 393 if (ret) 394 return ret; 395 396 /* 397 * It must generate STOP before read I2DR to prevent 398 * controller from generating another clock cycle 399 */ 400 if (i == (len - 1)) { 401 temp = readb(&i2c_regs->i2cr); 402 temp &= ~(I2CR_MSTA | I2CR_MTX); 403 writeb(temp, &i2c_regs->i2cr); 404 i2c_imx_bus_busy(0); 405 } else if (i == (len - 2)) { 406 temp = readb(&i2c_regs->i2cr); 407 temp |= I2CR_TX_NO_AK; 408 writeb(temp, &i2c_regs->i2cr); 409 } 410 411 buf[i] = readb(&i2c_regs->i2dr); 412 } 413 414 i2c_imx_stop(); 415 416 return ret; 417 } 418 419 /* 420 * Write data to I2C device 421 */ 422 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 423 { 424 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 425 int ret; 426 int i; 427 428 ret = i2c_imx_start(); 429 if (ret) 430 return ret; 431 432 /* write slave address */ 433 ret = i2c_imx_set_chip_addr(chip, 0); 434 if (ret) 435 return ret; 436 437 ret = i2c_imx_set_reg_addr(addr, alen); 438 if (ret) 439 return ret; 440 441 for (i = 0; i < len; i++) { 442 writeb(buf[i], &i2c_regs->i2dr); 443 444 ret = i2c_imx_trx_complete(); 445 if (ret) 446 return ret; 447 448 ret = i2c_imx_acked(); 449 if (ret) 450 return ret; 451 } 452 453 i2c_imx_stop(); 454 455 return ret; 456 } 457 #endif /* CONFIG_HARD_I2C */ 458