1 /* 2 * Driver for the TWSI (i2c) controller found on the Marvell 3 * orion5x and kirkwood SoC families. 4 * 5 * Author: Albert Aribaud <albert.u.boot@aribaud.net> 6 * Copyright (c) 2010 Albert Aribaud. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <asm/io.h> 15 #include <linux/compat.h> 16 #ifdef CONFIG_DM_I2C 17 #include <dm.h> 18 #endif 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 /* 23 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other 24 * settings 25 */ 26 27 #ifndef CONFIG_DM_I2C 28 #if defined(CONFIG_ORION5X) 29 #include <asm/arch/orion5x.h> 30 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) 31 #include <asm/arch/soc.h> 32 #elif defined(CONFIG_SUNXI) 33 #include <asm/arch/i2c.h> 34 #else 35 #error Driver mvtwsi not supported by SoC or board 36 #endif 37 #endif /* CONFIG_DM_I2C */ 38 39 /* 40 * TWSI register structure 41 */ 42 43 #ifdef CONFIG_SUNXI 44 45 struct mvtwsi_registers { 46 u32 slave_address; 47 u32 xtnd_slave_addr; 48 u32 data; 49 u32 control; 50 u32 status; 51 u32 baudrate; 52 u32 soft_reset; 53 }; 54 55 #else 56 57 struct mvtwsi_registers { 58 u32 slave_address; 59 u32 data; 60 u32 control; 61 union { 62 u32 status; /* When reading */ 63 u32 baudrate; /* When writing */ 64 }; 65 u32 xtnd_slave_addr; 66 u32 reserved[2]; 67 u32 soft_reset; 68 }; 69 70 #endif 71 72 #ifdef CONFIG_DM_I2C 73 struct mvtwsi_i2c_dev { 74 /* TWSI Register base for the device */ 75 struct mvtwsi_registers *base; 76 /* Number of the device (determined from cell-index property) */ 77 int index; 78 /* The I2C slave address for the device */ 79 u8 slaveadd; 80 /* The configured I2C speed in Hz */ 81 uint speed; 82 /* The current length of a clock period (depending on speed) */ 83 uint tick; 84 }; 85 #endif /* CONFIG_DM_I2C */ 86 87 /* 88 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control 89 * register 90 */ 91 enum mvtwsi_ctrl_register_fields { 92 /* Acknowledge bit */ 93 MVTWSI_CONTROL_ACK = 0x00000004, 94 /* Interrupt flag */ 95 MVTWSI_CONTROL_IFLG = 0x00000008, 96 /* Stop bit */ 97 MVTWSI_CONTROL_STOP = 0x00000010, 98 /* Start bit */ 99 MVTWSI_CONTROL_START = 0x00000020, 100 /* I2C enable */ 101 MVTWSI_CONTROL_TWSIEN = 0x00000040, 102 /* Interrupt enable */ 103 MVTWSI_CONTROL_INTEN = 0x00000080, 104 }; 105 106 /* 107 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1; 108 * on other platforms, it is a normal r/w bit, which is cleared by writing 0. 109 */ 110 111 #ifdef CONFIG_SUNXI_GEN_SUN6I 112 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 113 #else 114 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 115 #endif 116 117 /* 118 * enum mvstwsi_status_values - Possible values of I2C controller's status 119 * register 120 * 121 * Only those statuses expected in normal master operation on 122 * non-10-bit-address devices are specified. 123 * 124 * Every status that's unexpected during normal operation (bus errors, 125 * arbitration losses, missing ACKs...) is passed back to the caller as an error 126 * code. 127 */ 128 enum mvstwsi_status_values { 129 /* START condition transmitted */ 130 MVTWSI_STATUS_START = 0x08, 131 /* Repeated START condition transmitted */ 132 MVTWSI_STATUS_REPEATED_START = 0x10, 133 /* Address + write bit transmitted, ACK received */ 134 MVTWSI_STATUS_ADDR_W_ACK = 0x18, 135 /* Data transmitted, ACK received */ 136 MVTWSI_STATUS_DATA_W_ACK = 0x28, 137 /* Address + read bit transmitted, ACK received */ 138 MVTWSI_STATUS_ADDR_R_ACK = 0x40, 139 /* Address + read bit transmitted, ACK not received */ 140 MVTWSI_STATUS_ADDR_R_NAK = 0x48, 141 /* Data received, ACK transmitted */ 142 MVTWSI_STATUS_DATA_R_ACK = 0x50, 143 /* Data received, ACK not transmitted */ 144 MVTWSI_STATUS_DATA_R_NAK = 0x58, 145 /* No relevant status */ 146 MVTWSI_STATUS_IDLE = 0xF8, 147 }; 148 149 /* 150 * enum mvstwsi_ack_flags - Determine whether a read byte should be 151 * acknowledged or not. 152 */ 153 enum mvtwsi_ack_flags { 154 /* Send NAK after received byte */ 155 MVTWSI_READ_NAK = 0, 156 /* Send ACK after received byte */ 157 MVTWSI_READ_ACK = 1, 158 }; 159 160 inline uint calc_tick(uint speed) 161 { 162 /* One tick = the duration of a period at the specified speed in ns (we 163 * add 100 ns to be on the safe side) */ 164 return (1000000000u / speed) + 100; 165 } 166 167 #ifndef CONFIG_DM_I2C 168 169 /* 170 * MVTWSI controller base 171 */ 172 173 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) 174 { 175 switch (adap->hwadapnr) { 176 #ifdef CONFIG_I2C_MVTWSI_BASE0 177 case 0: 178 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; 179 #endif 180 #ifdef CONFIG_I2C_MVTWSI_BASE1 181 case 1: 182 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; 183 #endif 184 #ifdef CONFIG_I2C_MVTWSI_BASE2 185 case 2: 186 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2; 187 #endif 188 #ifdef CONFIG_I2C_MVTWSI_BASE3 189 case 3: 190 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3; 191 #endif 192 #ifdef CONFIG_I2C_MVTWSI_BASE4 193 case 4: 194 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4; 195 #endif 196 #ifdef CONFIG_I2C_MVTWSI_BASE5 197 case 5: 198 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5; 199 #endif 200 default: 201 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); 202 break; 203 } 204 205 return NULL; 206 } 207 #endif 208 209 /* 210 * enum mvtwsi_error_class - types of I2C errors 211 */ 212 enum mvtwsi_error_class { 213 /* The controller returned a different status than expected */ 214 MVTWSI_ERROR_WRONG_STATUS = 0x01, 215 /* The controller timed out */ 216 MVTWSI_ERROR_TIMEOUT = 0x02, 217 }; 218 219 /* 220 * mvtwsi_error() - Build I2C return code from error information 221 * 222 * For debugging purposes, this function packs some information of an occurred 223 * error into a return code. These error codes are returned from I2C API 224 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.). 225 * 226 * @ec: The error class of the error (enum mvtwsi_error_class). 227 * @lc: The last value of the control register. 228 * @ls: The last value of the status register. 229 * @es: The expected value of the status register. 230 * @return The generated error code. 231 */ 232 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es) 233 { 234 return ((ec << 24) & 0xFF000000) 235 | ((lc << 16) & 0x00FF0000) 236 | ((ls << 8) & 0x0000FF00) 237 | (es & 0xFF); 238 } 239 240 /* 241 * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as 242 * expected, return 0 (ok) or 'wrong status' otherwise. 243 */ 244 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, 245 uint tick) 246 { 247 int control, status; 248 int timeout = 1000; 249 250 do { 251 control = readl(&twsi->control); 252 if (control & MVTWSI_CONTROL_IFLG) { 253 status = readl(&twsi->status); 254 if (status == expected_status) 255 return 0; 256 else 257 return mvtwsi_error( 258 MVTWSI_ERROR_WRONG_STATUS, 259 control, status, expected_status); 260 } 261 ndelay(tick); /* One clock cycle */ 262 } while (timeout--); 263 status = readl(&twsi->status); 264 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, 265 expected_status); 266 } 267 268 /* 269 * Assert the START condition, either in a single I2C transaction 270 * or inside back-to-back ones (repeated starts). 271 */ 272 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status, 273 uint tick) 274 { 275 /* Assert START */ 276 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START | 277 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 278 /* Wait for controller to process START */ 279 return twsi_wait(twsi, expected_status, tick); 280 } 281 282 /* 283 * Send a byte (i2c address or data). 284 */ 285 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte, 286 int expected_status, uint tick) 287 { 288 /* Write byte to data register for sending */ 289 writel(byte, &twsi->data); 290 /* Clear any pending interrupt -- that will cause sending */ 291 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG, 292 &twsi->control); 293 /* Wait for controller to receive byte, and check ACK */ 294 return twsi_wait(twsi, expected_status, tick); 295 } 296 297 /* 298 * Receive a byte. 299 */ 300 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag, 301 uint tick) 302 { 303 int expected_status, status, control; 304 305 /* Compute expected status based on passed ACK flag */ 306 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK : 307 MVTWSI_STATUS_DATA_R_NAK; 308 /* Acknowledge *previous state*, and launch receive */ 309 control = MVTWSI_CONTROL_TWSIEN; 310 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0; 311 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 312 /* Wait for controller to receive byte, and assert ACK or NAK */ 313 status = twsi_wait(twsi, expected_status, tick); 314 /* If we did receive the expected byte, store it */ 315 if (status == 0) 316 *byte = readl(&twsi->data); 317 return status; 318 } 319 320 /* 321 * Assert the STOP condition. 322 * This is also used to force the bus back to idle (SDA = SCL = 1). 323 */ 324 static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) 325 { 326 int control, stop_status; 327 int status = 0; 328 int timeout = 1000; 329 330 /* Assert STOP */ 331 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; 332 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 333 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */ 334 do { 335 stop_status = readl(&twsi->status); 336 if (stop_status == MVTWSI_STATUS_IDLE) 337 break; 338 ndelay(tick); /* One clock cycle */ 339 } while (timeout--); 340 control = readl(&twsi->control); 341 if (stop_status != MVTWSI_STATUS_IDLE) 342 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT, 343 control, status, MVTWSI_STATUS_IDLE); 344 return status; 345 } 346 347 static uint twsi_calc_freq(const int n, const int m) 348 { 349 #ifdef CONFIG_SUNXI 350 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); 351 #else 352 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); 353 #endif 354 } 355 356 /* 357 * Reset controller. 358 * Controller reset also resets the baud rate and slave address, so 359 * they must be re-established afterwards. 360 */ 361 static void twsi_reset(struct mvtwsi_registers *twsi) 362 { 363 /* Reset controller */ 364 writel(0, &twsi->soft_reset); 365 /* Wait 2 ms -- this is what the Marvell LSP does */ 366 udelay(20000); 367 } 368 369 /* 370 * Sets baud to the highest possible value not exceeding the requested one. 371 */ 372 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi, 373 uint requested_speed) 374 { 375 uint tmp_speed, highest_speed, n, m; 376 uint baud = 0x44; /* Baud rate after controller reset */ 377 378 highest_speed = 0; 379 /* Successively try m, n combinations, and use the combination 380 * resulting in the largest speed that's not above the requested 381 * speed */ 382 for (n = 0; n < 8; n++) { 383 for (m = 0; m < 16; m++) { 384 tmp_speed = twsi_calc_freq(n, m); 385 if ((tmp_speed <= requested_speed) && 386 (tmp_speed > highest_speed)) { 387 highest_speed = tmp_speed; 388 baud = (m << 3) | n; 389 } 390 } 391 } 392 writel(baud, &twsi->baudrate); 393 394 /* Wait for controller for one tick */ 395 #ifdef CONFIG_DM_I2C 396 ndelay(calc_tick(highest_speed)); 397 #else 398 ndelay(10000); 399 #endif 400 return highest_speed; 401 } 402 403 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, 404 int slaveadd, uint *actual_speed) 405 { 406 /* Reset controller */ 407 twsi_reset(twsi); 408 /* Set speed */ 409 *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed); 410 /* Set slave address; even though we don't use it */ 411 writel(slaveadd, &twsi->slave_address); 412 writel(0, &twsi->xtnd_slave_addr); 413 /* Assert STOP, but don't care for the result */ 414 #ifdef CONFIG_DM_I2C 415 (void) twsi_stop(twsi, calc_tick(*actual_speed)); 416 #else 417 (void) twsi_stop(twsi, 10000); 418 #endif 419 } 420 421 /* 422 * Begin I2C transaction with expected start status, at given address. 423 * Expected address status will derive from direction bit (bit 0) in addr. 424 */ 425 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status, 426 u8 addr, uint tick) 427 { 428 int status, expected_addr_status; 429 430 /* Compute the expected address status from the direction bit in 431 * the address byte */ 432 if (addr & 1) /* Reading */ 433 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; 434 else /* Writing */ 435 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; 436 /* Assert START */ 437 status = twsi_start(twsi, expected_start_status, tick); 438 /* Send out the address if the start went well */ 439 if (status == 0) 440 status = twsi_send(twsi, addr, expected_addr_status, tick); 441 /* Return 0, or the status of the first failure */ 442 return status; 443 } 444 445 /* 446 * Begin read, nak data byte, end. 447 */ 448 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip, 449 uint tick) 450 { 451 u8 dummy_byte; 452 int status; 453 454 /* Begin i2c read */ 455 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick); 456 /* Dummy read was accepted: receive byte, but NAK it. */ 457 if (status == 0) 458 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick); 459 /* Stop transaction */ 460 twsi_stop(twsi, tick); 461 /* Return 0, or the status of the first failure */ 462 return status; 463 } 464 465 /* 466 * Begin write, send address byte(s), begin read, receive data bytes, end. 467 * 468 * NOTE: Some devices want a stop right before the second start, while some 469 * will choke if it is there. Since deciding this is not yet supported in 470 * higher level APIs, we need to make a decision here, and for the moment that 471 * will be a repeated start without a preceding stop. 472 */ 473 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, 474 u8 *addr, int alen, uchar *data, int length, 475 uint tick) 476 { 477 int status = 0; 478 int stop_status; 479 int expected_start = MVTWSI_STATUS_START; 480 481 if (alen > 0) { 482 /* Begin i2c write to send the address bytes */ 483 status = i2c_begin(twsi, expected_start, (chip << 1), tick); 484 /* Send address bytes */ 485 while ((status == 0) && alen--) 486 status = twsi_send(twsi, *(addr++), 487 MVTWSI_STATUS_DATA_W_ACK, tick); 488 /* Send repeated STARTs after the initial START */ 489 expected_start = MVTWSI_STATUS_REPEATED_START; 490 } 491 /* Begin i2c read to receive data bytes */ 492 if (status == 0) 493 status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick); 494 /* Receive actual data bytes; set NAK if we if we have nothing more to 495 * read */ 496 while ((status == 0) && length--) 497 status = twsi_recv(twsi, data++, 498 length > 0 ? 499 MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick); 500 /* Stop transaction */ 501 stop_status = twsi_stop(twsi, tick); 502 /* Return 0, or the status of the first failure */ 503 return status != 0 ? status : stop_status; 504 } 505 506 /* 507 * Begin write, send address byte(s), send data bytes, end. 508 */ 509 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, 510 u8 *addr, int alen, uchar *data, int length, 511 uint tick) 512 { 513 int status, stop_status; 514 515 /* Begin i2c write to send first the address bytes, then the 516 * data bytes */ 517 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick); 518 /* Send address bytes */ 519 while ((status == 0) && (alen-- > 0)) 520 status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK, 521 tick); 522 /* Send data bytes */ 523 while ((status == 0) && (length-- > 0)) 524 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK, 525 tick); 526 /* Stop transaction */ 527 stop_status = twsi_stop(twsi, tick); 528 /* Return 0, or the status of the first failure */ 529 return status != 0 ? status : stop_status; 530 } 531 532 #ifndef CONFIG_DM_I2C 533 static void twsi_i2c_init(struct i2c_adapter *adap, int speed, 534 int slaveadd) 535 { 536 struct mvtwsi_registers *twsi = twsi_get_base(adap); 537 __twsi_i2c_init(twsi, speed, slaveadd, NULL); 538 } 539 540 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap, 541 uint requested_speed) 542 { 543 struct mvtwsi_registers *twsi = twsi_get_base(adap); 544 __twsi_i2c_set_bus_speed(twsi, requested_speed); 545 return 0; 546 } 547 548 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) 549 { 550 struct mvtwsi_registers *twsi = twsi_get_base(adap); 551 return __twsi_i2c_probe_chip(twsi, chip, 10000); 552 } 553 554 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 555 int alen, uchar *data, int length) 556 { 557 struct mvtwsi_registers *twsi = twsi_get_base(adap); 558 u8 addr_bytes[4]; 559 560 addr_bytes[0] = (addr >> 0) & 0xFF; 561 addr_bytes[1] = (addr >> 8) & 0xFF; 562 addr_bytes[2] = (addr >> 16) & 0xFF; 563 addr_bytes[3] = (addr >> 24) & 0xFF; 564 565 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length, 566 10000); 567 } 568 569 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 570 int alen, uchar *data, int length) 571 { 572 struct mvtwsi_registers *twsi = twsi_get_base(adap); 573 u8 addr_bytes[4]; 574 575 addr_bytes[0] = (addr >> 0) & 0xFF; 576 addr_bytes[1] = (addr >> 8) & 0xFF; 577 addr_bytes[2] = (addr >> 16) & 0xFF; 578 addr_bytes[3] = (addr >> 24) & 0xFF; 579 580 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length, 581 10000); 582 } 583 584 #ifdef CONFIG_I2C_MVTWSI_BASE0 585 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, 586 twsi_i2c_read, twsi_i2c_write, 587 twsi_i2c_set_bus_speed, 588 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 589 #endif 590 #ifdef CONFIG_I2C_MVTWSI_BASE1 591 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, 592 twsi_i2c_read, twsi_i2c_write, 593 twsi_i2c_set_bus_speed, 594 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) 595 596 #endif 597 #ifdef CONFIG_I2C_MVTWSI_BASE2 598 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe, 599 twsi_i2c_read, twsi_i2c_write, 600 twsi_i2c_set_bus_speed, 601 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) 602 603 #endif 604 #ifdef CONFIG_I2C_MVTWSI_BASE3 605 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe, 606 twsi_i2c_read, twsi_i2c_write, 607 twsi_i2c_set_bus_speed, 608 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) 609 610 #endif 611 #ifdef CONFIG_I2C_MVTWSI_BASE4 612 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, 613 twsi_i2c_read, twsi_i2c_write, 614 twsi_i2c_set_bus_speed, 615 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) 616 617 #endif 618 #ifdef CONFIG_I2C_MVTWSI_BASE5 619 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, 620 twsi_i2c_read, twsi_i2c_write, 621 twsi_i2c_set_bus_speed, 622 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) 623 624 #endif 625 #else /* CONFIG_DM_I2C */ 626 627 static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 628 u32 chip_flags) 629 { 630 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 631 return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick); 632 } 633 634 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed) 635 { 636 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 637 638 dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed); 639 dev->tick = calc_tick(dev->speed); 640 641 return 0; 642 } 643 644 static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus) 645 { 646 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 647 648 dev->base = dev_get_addr_ptr(bus); 649 650 if (!dev->base) 651 return -ENOMEM; 652 653 dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 654 "cell-index", -1); 655 dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 656 "u-boot,i2c-slave-addr", 0x0); 657 dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 658 "clock-frequency", 100000); 659 return 0; 660 } 661 662 static int mvtwsi_i2c_probe(struct udevice *bus) 663 { 664 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 665 uint actual_speed; 666 667 __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); 668 dev->speed = actual_speed; 669 dev->tick = calc_tick(dev->speed); 670 return 0; 671 } 672 673 static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 674 { 675 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 676 struct i2c_msg *dmsg, *omsg, dummy; 677 678 memset(&dummy, 0, sizeof(struct i2c_msg)); 679 680 /* We expect either two messages (one with an offset and one with the 681 * actual data) or one message (just data or offset/data combined) */ 682 if (nmsgs > 2 || nmsgs == 0) { 683 debug("%s: Only one or two messages are supported.", __func__); 684 return -1; 685 } 686 687 omsg = nmsgs == 1 ? &dummy : msg; 688 dmsg = nmsgs == 1 ? msg : msg + 1; 689 690 if (dmsg->flags & I2C_M_RD) 691 return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf, 692 omsg->len, dmsg->buf, dmsg->len, 693 dev->tick); 694 else 695 return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf, 696 omsg->len, dmsg->buf, dmsg->len, 697 dev->tick); 698 } 699 700 static const struct dm_i2c_ops mvtwsi_i2c_ops = { 701 .xfer = mvtwsi_i2c_xfer, 702 .probe_chip = mvtwsi_i2c_probe_chip, 703 .set_bus_speed = mvtwsi_i2c_set_bus_speed, 704 }; 705 706 static const struct udevice_id mvtwsi_i2c_ids[] = { 707 { .compatible = "marvell,mv64xxx-i2c", }, 708 { /* sentinel */ } 709 }; 710 711 U_BOOT_DRIVER(i2c_mvtwsi) = { 712 .name = "i2c_mvtwsi", 713 .id = UCLASS_I2C, 714 .of_match = mvtwsi_i2c_ids, 715 .probe = mvtwsi_i2c_probe, 716 .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata, 717 .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev), 718 .ops = &mvtwsi_i2c_ops, 719 }; 720 #endif /* CONFIG_DM_I2C */ 721