1 /* 2 * Driver for the TWSI (i2c) controller found on the Marvell 3 * orion5x and kirkwood SoC families. 4 * 5 * Author: Albert Aribaud <albert.u.boot@aribaud.net> 6 * Copyright (c) 2010 Albert Aribaud. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <asm/io.h> 15 16 /* 17 * include a file that will provide CONFIG_I2C_MVTWSI_BASE* 18 * and possibly other settings 19 */ 20 21 #if defined(CONFIG_ORION5X) 22 #include <asm/arch/orion5x.h> 23 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) 24 #include <asm/arch/soc.h> 25 #elif defined(CONFIG_SUNXI) 26 #include <asm/arch/i2c.h> 27 #else 28 #error Driver mvtwsi not supported by SoC or board 29 #endif 30 31 /* 32 * TWSI register structure 33 */ 34 35 #ifdef CONFIG_SUNXI 36 37 struct mvtwsi_registers { 38 u32 slave_address; 39 u32 xtnd_slave_addr; 40 u32 data; 41 u32 control; 42 u32 status; 43 u32 baudrate; 44 u32 soft_reset; 45 }; 46 47 #else 48 49 struct mvtwsi_registers { 50 u32 slave_address; 51 u32 data; 52 u32 control; 53 union { 54 u32 status; /* when reading */ 55 u32 baudrate; /* when writing */ 56 }; 57 u32 xtnd_slave_addr; 58 u32 reserved[2]; 59 u32 soft_reset; 60 }; 61 62 #endif 63 64 /* 65 * Control register fields 66 */ 67 68 #define MVTWSI_CONTROL_ACK 0x00000004 69 #define MVTWSI_CONTROL_IFLG 0x00000008 70 #define MVTWSI_CONTROL_STOP 0x00000010 71 #define MVTWSI_CONTROL_START 0x00000020 72 #define MVTWSI_CONTROL_TWSIEN 0x00000040 73 #define MVTWSI_CONTROL_INTEN 0x00000080 74 75 /* 76 * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1, 77 * on other platforms it is a normal r/w bit which is cleared by writing 0. 78 */ 79 80 #ifdef CONFIG_SUNXI_GEN_SUN6I 81 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 82 #else 83 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 84 #endif 85 86 /* 87 * Status register values -- only those expected in normal master 88 * operation on non-10-bit-address devices; whatever status we don't 89 * expect in nominal conditions (bus errors, arbitration losses, 90 * missing ACKs...) we just pass back to the caller as an error 91 * code. 92 */ 93 94 #define MVTWSI_STATUS_START 0x08 95 #define MVTWSI_STATUS_REPEATED_START 0x10 96 #define MVTWSI_STATUS_ADDR_W_ACK 0x18 97 #define MVTWSI_STATUS_DATA_W_ACK 0x28 98 #define MVTWSI_STATUS_ADDR_R_ACK 0x40 99 #define MVTWSI_STATUS_ADDR_R_NAK 0x48 100 #define MVTWSI_STATUS_DATA_R_ACK 0x50 101 #define MVTWSI_STATUS_DATA_R_NAK 0x58 102 #define MVTWSI_STATUS_IDLE 0xF8 103 104 /* 105 * MVTWSI controller base 106 */ 107 108 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) 109 { 110 switch (adap->hwadapnr) { 111 #ifdef CONFIG_I2C_MVTWSI_BASE0 112 case 0: 113 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0; 114 #endif 115 #ifdef CONFIG_I2C_MVTWSI_BASE1 116 case 1: 117 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1; 118 #endif 119 #ifdef CONFIG_I2C_MVTWSI_BASE2 120 case 2: 121 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2; 122 #endif 123 #ifdef CONFIG_I2C_MVTWSI_BASE3 124 case 3: 125 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3; 126 #endif 127 #ifdef CONFIG_I2C_MVTWSI_BASE4 128 case 4: 129 return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4; 130 #endif 131 default: 132 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); 133 break; 134 } 135 136 return NULL; 137 } 138 139 /* 140 * Returned statuses are 0 for success and nonzero otherwise. 141 * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. 142 * Thus to ease debugging, the return status contains some debug info: 143 * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'. 144 * - bits 23..16 are the last value of the control register. 145 * - bits 15..8 are the last value of the status register. 146 * - bits 7..0 are the expected value of the status register. 147 */ 148 149 #define MVTWSI_ERROR_WRONG_STATUS 0x01 150 #define MVTWSI_ERROR_TIMEOUT 0x02 151 152 #define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \ 153 ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF)) 154 155 /* 156 * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, 157 * return 0 (ok) or return 'wrong status'. 158 */ 159 static int twsi_wait(struct i2c_adapter *adap, int expected_status) 160 { 161 struct mvtwsi_registers *twsi = twsi_get_base(adap); 162 int control, status; 163 int timeout = 1000; 164 165 do { 166 control = readl(&twsi->control); 167 if (control & MVTWSI_CONTROL_IFLG) { 168 status = readl(&twsi->status); 169 if (status == expected_status) 170 return 0; 171 else 172 return MVTWSI_ERROR( 173 MVTWSI_ERROR_WRONG_STATUS, 174 control, status, expected_status); 175 } 176 udelay(10); /* one clock cycle at 100 kHz */ 177 } while (timeout--); 178 status = readl(&twsi->status); 179 return MVTWSI_ERROR( 180 MVTWSI_ERROR_TIMEOUT, control, status, expected_status); 181 } 182 183 /* 184 * These flags are ORed to any write to the control register 185 * They allow global setting of TWSIEN and ACK. 186 * By default none are set. 187 * twsi_start() sets TWSIEN (in case the controller was disabled) 188 * twsi_recv() sets ACK or resets it depending on expected status. 189 */ 190 static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; 191 192 /* 193 * Assert the START condition, either in a single I2C transaction 194 * or inside back-to-back ones (repeated starts). 195 */ 196 static int twsi_start(struct i2c_adapter *adap, int expected_status) 197 { 198 struct mvtwsi_registers *twsi = twsi_get_base(adap); 199 200 /* globally set TWSIEN in case it was not */ 201 twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; 202 /* assert START */ 203 twsi_control_flags |= MVTWSI_CONTROL_START | MVTWSI_CONTROL_CLEAR_IFLG; 204 writel(twsi_control_flags, &twsi->control); 205 /* wait for controller to process START */ 206 return twsi_wait(adap, expected_status); 207 } 208 209 /* 210 * Send a byte (i2c address or data). 211 */ 212 static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status) 213 { 214 struct mvtwsi_registers *twsi = twsi_get_base(adap); 215 216 /* put byte in data register for sending */ 217 writel(byte, &twsi->data); 218 /* clear any pending interrupt -- that'll cause sending */ 219 writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 220 /* wait for controller to receive byte and check ACK */ 221 return twsi_wait(adap, expected_status); 222 } 223 224 /* 225 * Receive a byte. 226 * Global mvtwsi_control_flags variable says if we should ack or nak. 227 */ 228 static int twsi_recv(struct i2c_adapter *adap, u8 *byte) 229 { 230 struct mvtwsi_registers *twsi = twsi_get_base(adap); 231 int expected_status, status; 232 233 /* compute expected status based on ACK bit in global control flags */ 234 if (twsi_control_flags & MVTWSI_CONTROL_ACK) 235 expected_status = MVTWSI_STATUS_DATA_R_ACK; 236 else 237 expected_status = MVTWSI_STATUS_DATA_R_NAK; 238 /* acknowledge *previous state* and launch receive */ 239 writel(twsi_control_flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 240 /* wait for controller to receive byte and assert ACK or NAK */ 241 status = twsi_wait(adap, expected_status); 242 /* if we did receive expected byte then store it */ 243 if (status == 0) 244 *byte = readl(&twsi->data); 245 /* return status */ 246 return status; 247 } 248 249 /* 250 * Assert the STOP condition. 251 * This is also used to force the bus back in idle (SDA=SCL=1). 252 */ 253 static int twsi_stop(struct i2c_adapter *adap, int status) 254 { 255 struct mvtwsi_registers *twsi = twsi_get_base(adap); 256 int control, stop_status; 257 int timeout = 1000; 258 259 /* assert STOP */ 260 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; 261 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 262 /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ 263 do { 264 stop_status = readl(&twsi->status); 265 if (stop_status == MVTWSI_STATUS_IDLE) 266 break; 267 udelay(10); /* one clock cycle at 100 kHz */ 268 } while (timeout--); 269 control = readl(&twsi->control); 270 if (stop_status != MVTWSI_STATUS_IDLE) 271 if (status == 0) 272 status = MVTWSI_ERROR( 273 MVTWSI_ERROR_TIMEOUT, 274 control, status, MVTWSI_STATUS_IDLE); 275 return status; 276 } 277 278 static unsigned int twsi_calc_freq(const int n, const int m) 279 { 280 #ifdef CONFIG_SUNXI 281 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); 282 #else 283 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); 284 #endif 285 } 286 287 /* 288 * Reset controller. 289 * Controller reset also resets the baud rate and slave address, so 290 * they must be re-established afterwards. 291 */ 292 static void twsi_reset(struct i2c_adapter *adap) 293 { 294 struct mvtwsi_registers *twsi = twsi_get_base(adap); 295 /* ensure controller will be enabled by any twsi*() function */ 296 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; 297 /* reset controller */ 298 writel(0, &twsi->soft_reset); 299 /* wait 2 ms -- this is what the Marvell LSP does */ 300 udelay(20000); 301 } 302 303 /* 304 * I2C init called by cmd_i2c when doing 'i2c reset'. 305 * Sets baud to the highest possible value not exceeding requested one. 306 */ 307 static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap, 308 unsigned int requested_speed) 309 { 310 struct mvtwsi_registers *twsi = twsi_get_base(adap); 311 unsigned int tmp_speed, highest_speed, n, m; 312 unsigned int baud = 0x44; /* baudrate at controller reset */ 313 314 /* use actual speed to collect progressively higher values */ 315 highest_speed = 0; 316 /* compute m, n setting for highest speed not above requested speed */ 317 for (n = 0; n < 8; n++) { 318 for (m = 0; m < 16; m++) { 319 tmp_speed = twsi_calc_freq(n, m); 320 if ((tmp_speed <= requested_speed) 321 && (tmp_speed > highest_speed)) { 322 highest_speed = tmp_speed; 323 baud = (m << 3) | n; 324 } 325 } 326 } 327 writel(baud, &twsi->baudrate); 328 return 0; 329 } 330 331 static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 332 { 333 struct mvtwsi_registers *twsi = twsi_get_base(adap); 334 335 /* reset controller */ 336 twsi_reset(adap); 337 /* set speed */ 338 twsi_i2c_set_bus_speed(adap, speed); 339 /* set slave address even though we don't use it */ 340 writel(slaveadd, &twsi->slave_address); 341 writel(0, &twsi->xtnd_slave_addr); 342 /* assert STOP but don't care for the result */ 343 (void) twsi_stop(adap, 0); 344 } 345 346 /* 347 * Begin I2C transaction with expected start status, at given address. 348 * Common to i2c_probe, i2c_read and i2c_write. 349 * Expected address status will derive from direction bit (bit 0) in addr. 350 */ 351 static int i2c_begin(struct i2c_adapter *adap, int expected_start_status, 352 u8 addr) 353 { 354 int status, expected_addr_status; 355 356 /* compute expected address status from direction bit in addr */ 357 if (addr & 1) /* reading */ 358 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; 359 else /* writing */ 360 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; 361 /* assert START */ 362 status = twsi_start(adap, expected_start_status); 363 /* send out the address if the start went well */ 364 if (status == 0) 365 status = twsi_send(adap, addr, expected_addr_status); 366 /* return ok or status of first failure to caller */ 367 return status; 368 } 369 370 /* 371 * I2C probe called by cmd_i2c when doing 'i2c probe'. 372 * Begin read, nak data byte, end. 373 */ 374 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) 375 { 376 u8 dummy_byte; 377 int status; 378 379 /* begin i2c read */ 380 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1); 381 /* dummy read was accepted: receive byte but NAK it. */ 382 if (status == 0) 383 status = twsi_recv(adap, &dummy_byte); 384 /* Stop transaction */ 385 twsi_stop(adap, 0); 386 /* return 0 or status of first failure */ 387 return status; 388 } 389 390 /* 391 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c 392 * Begin write, send address byte(s), begin read, receive data bytes, end. 393 * 394 * NOTE: some EEPROMS want a stop right before the second start, while 395 * some will choke if it is there. Deciding which we should do is eeprom 396 * stuff, not i2c, but at the moment the APIs won't let us put it in 397 * cmd_eeprom, so we have to choose here, and for the moment that'll be 398 * a repeated start without a preceding stop. 399 */ 400 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 401 int alen, uchar *data, int length) 402 { 403 int status; 404 405 /* begin i2c write to send the address bytes */ 406 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1)); 407 /* send addr bytes */ 408 while ((status == 0) && alen--) 409 status = twsi_send(adap, addr >> (8*alen), 410 MVTWSI_STATUS_DATA_W_ACK); 411 /* begin i2c read to receive eeprom data bytes */ 412 if (status == 0) 413 status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START, 414 (chip << 1) | 1); 415 /* prepare ACK if at least one byte must be received */ 416 if (length > 0) 417 twsi_control_flags |= MVTWSI_CONTROL_ACK; 418 /* now receive actual bytes */ 419 while ((status == 0) && length--) { 420 /* reset NAK if we if no more to read now */ 421 if (length == 0) 422 twsi_control_flags &= ~MVTWSI_CONTROL_ACK; 423 /* read current byte */ 424 status = twsi_recv(adap, data++); 425 } 426 /* Stop transaction */ 427 status = twsi_stop(adap, status); 428 /* return 0 or status of first failure */ 429 return status; 430 } 431 432 /* 433 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c 434 * Begin write, send address byte(s), send data bytes, end. 435 */ 436 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 437 int alen, uchar *data, int length) 438 { 439 int status; 440 441 /* begin i2c write to send the eeprom adress bytes then data bytes */ 442 status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1)); 443 /* send addr bytes */ 444 while ((status == 0) && alen--) 445 status = twsi_send(adap, addr >> (8*alen), 446 MVTWSI_STATUS_DATA_W_ACK); 447 /* send data bytes */ 448 while ((status == 0) && (length-- > 0)) 449 status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK); 450 /* Stop transaction */ 451 status = twsi_stop(adap, status); 452 /* return 0 or status of first failure */ 453 return status; 454 } 455 456 #ifdef CONFIG_I2C_MVTWSI_BASE0 457 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, 458 twsi_i2c_read, twsi_i2c_write, 459 twsi_i2c_set_bus_speed, 460 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 461 #endif 462 #ifdef CONFIG_I2C_MVTWSI_BASE1 463 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, 464 twsi_i2c_read, twsi_i2c_write, 465 twsi_i2c_set_bus_speed, 466 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) 467 468 #endif 469 #ifdef CONFIG_I2C_MVTWSI_BASE2 470 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe, 471 twsi_i2c_read, twsi_i2c_write, 472 twsi_i2c_set_bus_speed, 473 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) 474 475 #endif 476 #ifdef CONFIG_I2C_MVTWSI_BASE3 477 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe, 478 twsi_i2c_read, twsi_i2c_write, 479 twsi_i2c_set_bus_speed, 480 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) 481 482 #endif 483 #ifdef CONFIG_I2C_MVTWSI_BASE4 484 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, 485 twsi_i2c_read, twsi_i2c_write, 486 twsi_i2c_set_bus_speed, 487 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) 488 489 #endif 490