1 /* 2 * Driver for the TWSI (i2c) controller found on the Marvell 3 * orion5x and kirkwood SoC families. 4 * 5 * Author: Albert Aribaud <albert.u.boot@aribaud.net> 6 * Copyright (c) 2010 Albert Aribaud. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <i2c.h> 13 #include <asm/errno.h> 14 #include <asm/io.h> 15 #ifdef CONFIG_DM_I2C 16 #include <dm.h> 17 #endif 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 /* 22 * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other 23 * settings 24 */ 25 26 #ifndef CONFIG_DM_I2C 27 #if defined(CONFIG_ORION5X) 28 #include <asm/arch/orion5x.h> 29 #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) 30 #include <asm/arch/soc.h> 31 #elif defined(CONFIG_SUNXI) 32 #include <asm/arch/i2c.h> 33 #else 34 #error Driver mvtwsi not supported by SoC or board 35 #endif 36 #endif /* CONFIG_DM_I2C */ 37 38 /* 39 * TWSI register structure 40 */ 41 42 #ifdef CONFIG_SUNXI 43 44 struct mvtwsi_registers { 45 u32 slave_address; 46 u32 xtnd_slave_addr; 47 u32 data; 48 u32 control; 49 u32 status; 50 u32 baudrate; 51 u32 soft_reset; 52 }; 53 54 #else 55 56 struct mvtwsi_registers { 57 u32 slave_address; 58 u32 data; 59 u32 control; 60 union { 61 u32 status; /* When reading */ 62 u32 baudrate; /* When writing */ 63 }; 64 u32 xtnd_slave_addr; 65 u32 reserved[2]; 66 u32 soft_reset; 67 }; 68 69 #endif 70 71 #ifdef CONFIG_DM_I2C 72 struct mvtwsi_i2c_dev { 73 /* TWSI Register base for the device */ 74 struct mvtwsi_registers *base; 75 /* Number of the device (determined from cell-index property) */ 76 int index; 77 /* The I2C slave address for the device */ 78 u8 slaveadd; 79 /* The configured I2C speed in Hz */ 80 uint speed; 81 }; 82 #endif /* CONFIG_DM_I2C */ 83 84 /* 85 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control 86 * register 87 */ 88 enum mvtwsi_ctrl_register_fields { 89 /* Acknowledge bit */ 90 MVTWSI_CONTROL_ACK = 0x00000004, 91 /* Interrupt flag */ 92 MVTWSI_CONTROL_IFLG = 0x00000008, 93 /* Stop bit */ 94 MVTWSI_CONTROL_STOP = 0x00000010, 95 /* Start bit */ 96 MVTWSI_CONTROL_START = 0x00000020, 97 /* I2C enable */ 98 MVTWSI_CONTROL_TWSIEN = 0x00000040, 99 /* Interrupt enable */ 100 MVTWSI_CONTROL_INTEN = 0x00000080, 101 }; 102 103 /* 104 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1; 105 * on other platforms, it is a normal r/w bit, which is cleared by writing 0. 106 */ 107 108 #ifdef CONFIG_SUNXI_GEN_SUN6I 109 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 110 #else 111 #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 112 #endif 113 114 /* 115 * enum mvstwsi_status_values - Possible values of I2C controller's status 116 * register 117 * 118 * Only those statuses expected in normal master operation on 119 * non-10-bit-address devices are specified. 120 * 121 * Every status that's unexpected during normal operation (bus errors, 122 * arbitration losses, missing ACKs...) is passed back to the caller as an error 123 * code. 124 */ 125 enum mvstwsi_status_values { 126 /* START condition transmitted */ 127 MVTWSI_STATUS_START = 0x08, 128 /* Repeated START condition transmitted */ 129 MVTWSI_STATUS_REPEATED_START = 0x10, 130 /* Address + write bit transmitted, ACK received */ 131 MVTWSI_STATUS_ADDR_W_ACK = 0x18, 132 /* Data transmitted, ACK received */ 133 MVTWSI_STATUS_DATA_W_ACK = 0x28, 134 /* Address + read bit transmitted, ACK received */ 135 MVTWSI_STATUS_ADDR_R_ACK = 0x40, 136 /* Address + read bit transmitted, ACK not received */ 137 MVTWSI_STATUS_ADDR_R_NAK = 0x48, 138 /* Data received, ACK transmitted */ 139 MVTWSI_STATUS_DATA_R_ACK = 0x50, 140 /* Data received, ACK not transmitted */ 141 MVTWSI_STATUS_DATA_R_NAK = 0x58, 142 /* No relevant status */ 143 MVTWSI_STATUS_IDLE = 0xF8, 144 }; 145 146 /* 147 * enum mvstwsi_ack_flags - Determine whether a read byte should be 148 * acknowledged or not. 149 */ 150 enum mvtwsi_ack_flags { 151 /* Send NAK after received byte */ 152 MVTWSI_READ_NAK = 0, 153 /* Send ACK after received byte */ 154 MVTWSI_READ_ACK = 1, 155 }; 156 157 #ifndef CONFIG_DM_I2C 158 /* 159 * MVTWSI controller base 160 */ 161 162 static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) 163 { 164 switch (adap->hwadapnr) { 165 #ifdef CONFIG_I2C_MVTWSI_BASE0 166 case 0: 167 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; 168 #endif 169 #ifdef CONFIG_I2C_MVTWSI_BASE1 170 case 1: 171 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; 172 #endif 173 #ifdef CONFIG_I2C_MVTWSI_BASE2 174 case 2: 175 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2; 176 #endif 177 #ifdef CONFIG_I2C_MVTWSI_BASE3 178 case 3: 179 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3; 180 #endif 181 #ifdef CONFIG_I2C_MVTWSI_BASE4 182 case 4: 183 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4; 184 #endif 185 #ifdef CONFIG_I2C_MVTWSI_BASE5 186 case 5: 187 return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5; 188 #endif 189 default: 190 printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); 191 break; 192 } 193 194 return NULL; 195 } 196 #endif 197 198 /* 199 * enum mvtwsi_error_class - types of I2C errors 200 */ 201 enum mvtwsi_error_class { 202 /* The controller returned a different status than expected */ 203 MVTWSI_ERROR_WRONG_STATUS = 0x01, 204 /* The controller timed out */ 205 MVTWSI_ERROR_TIMEOUT = 0x02, 206 }; 207 208 /* 209 * mvtwsi_error() - Build I2C return code from error information 210 * 211 * For debugging purposes, this function packs some information of an occurred 212 * error into a return code. These error codes are returned from I2C API 213 * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.). 214 * 215 * @ec: The error class of the error (enum mvtwsi_error_class). 216 * @lc: The last value of the control register. 217 * @ls: The last value of the status register. 218 * @es: The expected value of the status register. 219 * @return The generated error code. 220 */ 221 inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es) 222 { 223 return ((ec << 24) & 0xFF000000) 224 | ((lc << 16) & 0x00FF0000) 225 | ((ls << 8) & 0x0000FF00) 226 | (es & 0xFF); 227 } 228 229 /* 230 * Wait for IFLG to raise, or return 'timeout.' Then, if the status is as 231 * expected, return 0 (ok) or 'wrong status' otherwise. 232 */ 233 static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status) 234 { 235 int control, status; 236 int timeout = 1000; 237 238 do { 239 control = readl(&twsi->control); 240 if (control & MVTWSI_CONTROL_IFLG) { 241 status = readl(&twsi->status); 242 if (status == expected_status) 243 return 0; 244 else 245 return mvtwsi_error( 246 MVTWSI_ERROR_WRONG_STATUS, 247 control, status, expected_status); 248 } 249 udelay(10); /* One clock cycle at 100 kHz */ 250 } while (timeout--); 251 status = readl(&twsi->status); 252 return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, 253 expected_status); 254 } 255 256 /* 257 * Assert the START condition, either in a single I2C transaction 258 * or inside back-to-back ones (repeated starts). 259 */ 260 static int twsi_start(struct mvtwsi_registers *twsi, int expected_status) 261 { 262 /* Assert START */ 263 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START | 264 MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 265 /* Wait for controller to process START */ 266 return twsi_wait(twsi, expected_status); 267 } 268 269 /* 270 * Send a byte (i2c address or data). 271 */ 272 static int twsi_send(struct mvtwsi_registers *twsi, u8 byte, 273 int expected_status) 274 { 275 /* Write byte to data register for sending */ 276 writel(byte, &twsi->data); 277 /* Clear any pending interrupt -- that will cause sending */ 278 writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG, 279 &twsi->control); 280 /* Wait for controller to receive byte, and check ACK */ 281 return twsi_wait(twsi, expected_status); 282 } 283 284 /* 285 * Receive a byte. 286 */ 287 static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag) 288 { 289 int expected_status, status, control; 290 291 /* Compute expected status based on passed ACK flag */ 292 expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK : 293 MVTWSI_STATUS_DATA_R_NAK; 294 /* Acknowledge *previous state*, and launch receive */ 295 control = MVTWSI_CONTROL_TWSIEN; 296 control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0; 297 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 298 /* Wait for controller to receive byte, and assert ACK or NAK */ 299 status = twsi_wait(twsi, expected_status); 300 /* If we did receive the expected byte, store it */ 301 if (status == 0) 302 *byte = readl(&twsi->data); 303 return status; 304 } 305 306 /* 307 * Assert the STOP condition. 308 * This is also used to force the bus back to idle (SDA = SCL = 1). 309 */ 310 static int twsi_stop(struct mvtwsi_registers *twsi) 311 { 312 int control, stop_status; 313 int status = 0; 314 int timeout = 1000; 315 316 /* Assert STOP */ 317 control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; 318 writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); 319 /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */ 320 do { 321 stop_status = readl(&twsi->status); 322 if (stop_status == MVTWSI_STATUS_IDLE) 323 break; 324 udelay(10); /* One clock cycle at 100 kHz */ 325 } while (timeout--); 326 control = readl(&twsi->control); 327 if (stop_status != MVTWSI_STATUS_IDLE) 328 status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT, 329 control, status, MVTWSI_STATUS_IDLE); 330 return status; 331 } 332 333 static uint twsi_calc_freq(const int n, const int m) 334 { 335 #ifdef CONFIG_SUNXI 336 return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); 337 #else 338 return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); 339 #endif 340 } 341 342 /* 343 * Reset controller. 344 * Controller reset also resets the baud rate and slave address, so 345 * they must be re-established afterwards. 346 */ 347 static void twsi_reset(struct mvtwsi_registers *twsi) 348 { 349 /* Reset controller */ 350 writel(0, &twsi->soft_reset); 351 /* Wait 2 ms -- this is what the Marvell LSP does */ 352 udelay(20000); 353 } 354 355 /* 356 * Sets baud to the highest possible value not exceeding the requested one. 357 */ 358 static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi, 359 uint requested_speed) 360 { 361 uint tmp_speed, highest_speed, n, m; 362 uint baud = 0x44; /* Baud rate after controller reset */ 363 364 highest_speed = 0; 365 /* Successively try m, n combinations, and use the combination 366 * resulting in the largest speed that's not above the requested 367 * speed */ 368 for (n = 0; n < 8; n++) { 369 for (m = 0; m < 16; m++) { 370 tmp_speed = twsi_calc_freq(n, m); 371 if ((tmp_speed <= requested_speed) && 372 (tmp_speed > highest_speed)) { 373 highest_speed = tmp_speed; 374 baud = (m << 3) | n; 375 } 376 } 377 } 378 writel(baud, &twsi->baudrate); 379 return 0; 380 } 381 382 static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, 383 int slaveadd) 384 { 385 /* Reset controller */ 386 twsi_reset(twsi); 387 /* Set speed */ 388 __twsi_i2c_set_bus_speed(twsi, speed); 389 /* Set slave address; even though we don't use it */ 390 writel(slaveadd, &twsi->slave_address); 391 writel(0, &twsi->xtnd_slave_addr); 392 /* Assert STOP, but don't care for the result */ 393 (void) twsi_stop(twsi); 394 } 395 396 /* 397 * Begin I2C transaction with expected start status, at given address. 398 * Expected address status will derive from direction bit (bit 0) in addr. 399 */ 400 static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status, 401 u8 addr) 402 { 403 int status, expected_addr_status; 404 405 /* Compute the expected address status from the direction bit in 406 * the address byte */ 407 if (addr & 1) /* Reading */ 408 expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; 409 else /* Writing */ 410 expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; 411 /* Assert START */ 412 status = twsi_start(twsi, expected_start_status); 413 /* Send out the address if the start went well */ 414 if (status == 0) 415 status = twsi_send(twsi, addr, expected_addr_status); 416 /* Return 0, or the status of the first failure */ 417 return status; 418 } 419 420 /* 421 * Begin read, nak data byte, end. 422 */ 423 static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip) 424 { 425 u8 dummy_byte; 426 int status; 427 428 /* Begin i2c read */ 429 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1); 430 /* Dummy read was accepted: receive byte, but NAK it. */ 431 if (status == 0) 432 status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK); 433 /* Stop transaction */ 434 twsi_stop(twsi); 435 /* Return 0, or the status of the first failure */ 436 return status; 437 } 438 439 /* 440 * Begin write, send address byte(s), begin read, receive data bytes, end. 441 * 442 * NOTE: Some devices want a stop right before the second start, while some 443 * will choke if it is there. Since deciding this is not yet supported in 444 * higher level APIs, we need to make a decision here, and for the moment that 445 * will be a repeated start without a preceding stop. 446 */ 447 static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, 448 u8 *addr, int alen, uchar *data, int length) 449 { 450 int status = 0; 451 int stop_status; 452 453 /* Begin i2c write to send the address bytes */ 454 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1)); 455 /* Send address bytes */ 456 while ((status == 0) && alen--) 457 status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK); 458 /* Begin i2c read to receive data bytes */ 459 if (status == 0) 460 status = i2c_begin(twsi, MVTWSI_STATUS_REPEATED_START, 461 (chip << 1) | 1); 462 /* Receive actual data bytes; set NAK if we if we have nothing more to 463 * read */ 464 while ((status == 0) && length--) 465 status = twsi_recv(twsi, data++, 466 length > 0 ? 467 MVTWSI_READ_ACK : MVTWSI_READ_NAK); 468 /* Stop transaction */ 469 stop_status = twsi_stop(twsi); 470 /* Return 0, or the status of the first failure */ 471 return status != 0 ? status : stop_status; 472 } 473 474 /* 475 * Begin write, send address byte(s), send data bytes, end. 476 */ 477 static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, 478 u8 *addr, int alen, uchar *data, int length) 479 { 480 int status, stop_status; 481 482 /* Begin i2c write to send first the address bytes, then the 483 * data bytes */ 484 status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1)); 485 /* Send address bytes */ 486 while ((status == 0) && (alen-- > 0)) 487 status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK); 488 /* Send data bytes */ 489 while ((status == 0) && (length-- > 0)) 490 status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK); 491 /* Stop transaction */ 492 stop_status = twsi_stop(twsi); 493 /* Return 0, or the status of the first failure */ 494 return status != 0 ? status : stop_status; 495 } 496 497 #ifndef CONFIG_DM_I2C 498 static void twsi_i2c_init(struct i2c_adapter *adap, int speed, 499 int slaveadd) 500 { 501 struct mvtwsi_registers *twsi = twsi_get_base(adap); 502 __twsi_i2c_init(twsi, speed, slaveadd); 503 } 504 505 static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap, 506 uint requested_speed) 507 { 508 struct mvtwsi_registers *twsi = twsi_get_base(adap); 509 return __twsi_i2c_set_bus_speed(twsi, requested_speed); 510 } 511 512 static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) 513 { 514 struct mvtwsi_registers *twsi = twsi_get_base(adap); 515 return __twsi_i2c_probe_chip(twsi, chip); 516 } 517 518 static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 519 int alen, uchar *data, int length) 520 { 521 struct mvtwsi_registers *twsi = twsi_get_base(adap); 522 u8 addr_bytes[4]; 523 524 addr_bytes[0] = (addr >> 0) & 0xFF; 525 addr_bytes[1] = (addr >> 8) & 0xFF; 526 addr_bytes[2] = (addr >> 16) & 0xFF; 527 addr_bytes[3] = (addr >> 24) & 0xFF; 528 529 return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length); 530 } 531 532 static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 533 int alen, uchar *data, int length) 534 { 535 struct mvtwsi_registers *twsi = twsi_get_base(adap); 536 u8 addr_bytes[4]; 537 538 addr_bytes[0] = (addr >> 0) & 0xFF; 539 addr_bytes[1] = (addr >> 8) & 0xFF; 540 addr_bytes[2] = (addr >> 16) & 0xFF; 541 addr_bytes[3] = (addr >> 24) & 0xFF; 542 543 return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length); 544 } 545 546 #ifdef CONFIG_I2C_MVTWSI_BASE0 547 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe, 548 twsi_i2c_read, twsi_i2c_write, 549 twsi_i2c_set_bus_speed, 550 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 551 #endif 552 #ifdef CONFIG_I2C_MVTWSI_BASE1 553 U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe, 554 twsi_i2c_read, twsi_i2c_write, 555 twsi_i2c_set_bus_speed, 556 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) 557 558 #endif 559 #ifdef CONFIG_I2C_MVTWSI_BASE2 560 U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe, 561 twsi_i2c_read, twsi_i2c_write, 562 twsi_i2c_set_bus_speed, 563 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) 564 565 #endif 566 #ifdef CONFIG_I2C_MVTWSI_BASE3 567 U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe, 568 twsi_i2c_read, twsi_i2c_write, 569 twsi_i2c_set_bus_speed, 570 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) 571 572 #endif 573 #ifdef CONFIG_I2C_MVTWSI_BASE4 574 U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe, 575 twsi_i2c_read, twsi_i2c_write, 576 twsi_i2c_set_bus_speed, 577 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4) 578 579 #endif 580 #ifdef CONFIG_I2C_MVTWSI_BASE5 581 U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, 582 twsi_i2c_read, twsi_i2c_write, 583 twsi_i2c_set_bus_speed, 584 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) 585 586 #endif 587 #else /* CONFIG_DM_I2C */ 588 589 static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 590 u32 chip_flags) 591 { 592 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 593 return __twsi_i2c_probe_chip(dev->base, chip_addr); 594 } 595 596 static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed) 597 { 598 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 599 return __twsi_i2c_set_bus_speed(dev->base, speed); 600 } 601 602 static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus) 603 { 604 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 605 606 dev->base = dev_get_addr_ptr(bus); 607 608 if (!dev->base) 609 return -ENOMEM; 610 611 dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 612 "cell-index", -1); 613 dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 614 "u-boot,i2c-slave-addr", 0x0); 615 dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset, 616 "clock-frequency", 100000); 617 return 0; 618 } 619 620 static int mvtwsi_i2c_probe(struct udevice *bus) 621 { 622 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 623 __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd); 624 return 0; 625 } 626 627 static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 628 { 629 struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); 630 struct i2c_msg *dmsg, *omsg, dummy; 631 632 memset(&dummy, 0, sizeof(struct i2c_msg)); 633 634 /* We expect either two messages (one with an offset and one with the 635 * actual data) or one message (just data or offset/data combined) */ 636 if (nmsgs > 2 || nmsgs == 0) { 637 debug("%s: Only one or two messages are supported.", __func__); 638 return -1; 639 } 640 641 omsg = nmsgs == 1 ? &dummy : msg; 642 dmsg = nmsgs == 1 ? msg : msg + 1; 643 644 if (dmsg->flags & I2C_M_RD) 645 return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf, 646 omsg->len, dmsg->buf, dmsg->len); 647 else 648 return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf, 649 omsg->len, dmsg->buf, dmsg->len); 650 } 651 652 static const struct dm_i2c_ops mvtwsi_i2c_ops = { 653 .xfer = mvtwsi_i2c_xfer, 654 .probe_chip = mvtwsi_i2c_probe_chip, 655 .set_bus_speed = mvtwsi_i2c_set_bus_speed, 656 }; 657 658 static const struct udevice_id mvtwsi_i2c_ids[] = { 659 { .compatible = "marvell,mv64xxx-i2c", }, 660 { /* sentinel */ } 661 }; 662 663 U_BOOT_DRIVER(i2c_mvtwsi) = { 664 .name = "i2c_mvtwsi", 665 .id = UCLASS_I2C, 666 .of_match = mvtwsi_i2c_ids, 667 .probe = mvtwsi_i2c_probe, 668 .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata, 669 .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev), 670 .ops = &mvtwsi_i2c_ops, 671 }; 672 #endif /* CONFIG_DM_I2C */ 673