1 /* 2 * (C) Copyright 2000 3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it 4 * 5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 6 * Marius Groeger <mgroeger@sysgo.de> 7 * 8 * (C) Copyright 2003 Pengutronix e.K. 9 * Robert Schwebel <r.schwebel@pengutronix.de> 10 * 11 * (C) Copyright 2011 Marvell Inc. 12 * Lei Wen <leiwen@marvell.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Back ported to the 8xx platform (from the 8260 platform) by 17 * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 18 */ 19 20 #include <common.h> 21 #include <dm.h> 22 #include <i2c.h> 23 #include <asm/io.h> 24 #include "mv_i2c.h" 25 26 /* All transfers are described by this data structure */ 27 struct mv_i2c_msg { 28 u8 condition; 29 u8 acknack; 30 u8 direction; 31 u8 data; 32 }; 33 34 #ifdef CONFIG_ARMADA_3700 35 /* Armada 3700 has no padding between the registers */ 36 struct mv_i2c { 37 u32 ibmr; 38 u32 idbr; 39 u32 icr; 40 u32 isr; 41 u32 isar; 42 }; 43 #else 44 struct mv_i2c { 45 u32 ibmr; 46 u32 pad0; 47 u32 idbr; 48 u32 pad1; 49 u32 icr; 50 u32 pad2; 51 u32 isr; 52 u32 pad3; 53 u32 isar; 54 }; 55 #endif 56 57 /* 58 * Dummy implementation that can be overwritten by a board 59 * specific function 60 */ 61 __weak void i2c_clk_enable(void) 62 { 63 } 64 65 /* 66 * i2c_reset: - reset the host controller 67 * 68 */ 69 static void i2c_reset(struct mv_i2c *base) 70 { 71 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ 72 writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ 73 udelay(100); 74 writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ 75 76 i2c_clk_enable(); 77 78 writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ 79 writel(I2C_ICR_INIT, &base->icr); /* set control reg values */ 80 writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ 81 writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */ 82 udelay(100); 83 } 84 85 /* 86 * i2c_isr_set_cleared: - wait until certain bits of the I2C status register 87 * are set and cleared 88 * 89 * @return: 1 in case of success, 0 means timeout (no match within 10 ms). 90 */ 91 static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask, 92 unsigned long cleared_mask) 93 { 94 int timeout = 1000, isr; 95 96 do { 97 isr = readl(&base->isr); 98 udelay(10); 99 if (timeout-- < 0) 100 return 0; 101 } while (((isr & set_mask) != set_mask) 102 || ((isr & cleared_mask) != 0)); 103 104 return 1; 105 } 106 107 /* 108 * i2c_transfer: - Transfer one byte over the i2c bus 109 * 110 * This function can tranfer a byte over the i2c bus in both directions. 111 * It is used by the public API functions. 112 * 113 * @return: 0: transfer successful 114 * -1: message is empty 115 * -2: transmit timeout 116 * -3: ACK missing 117 * -4: receive timeout 118 * -5: illegal parameters 119 * -6: bus is busy and couldn't be aquired 120 */ 121 static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg) 122 { 123 int ret; 124 125 if (!msg) 126 goto transfer_error_msg_empty; 127 128 switch (msg->direction) { 129 case I2C_WRITE: 130 /* check if bus is not busy */ 131 if (!i2c_isr_set_cleared(base, 0, ISR_IBB)) 132 goto transfer_error_bus_busy; 133 134 /* start transmission */ 135 writel(readl(&base->icr) & ~ICR_START, &base->icr); 136 writel(readl(&base->icr) & ~ICR_STOP, &base->icr); 137 writel(msg->data, &base->idbr); 138 if (msg->condition == I2C_COND_START) 139 writel(readl(&base->icr) | ICR_START, &base->icr); 140 if (msg->condition == I2C_COND_STOP) 141 writel(readl(&base->icr) | ICR_STOP, &base->icr); 142 if (msg->acknack == I2C_ACKNAK_SENDNAK) 143 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr); 144 if (msg->acknack == I2C_ACKNAK_SENDACK) 145 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr); 146 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr); 147 writel(readl(&base->icr) | ICR_TB, &base->icr); 148 149 /* transmit register empty? */ 150 if (!i2c_isr_set_cleared(base, ISR_ITE, 0)) 151 goto transfer_error_transmit_timeout; 152 153 /* clear 'transmit empty' state */ 154 writel(readl(&base->isr) | ISR_ITE, &base->isr); 155 156 /* wait for ACK from slave */ 157 if (msg->acknack == I2C_ACKNAK_WAITACK) 158 if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK)) 159 goto transfer_error_ack_missing; 160 break; 161 162 case I2C_READ: 163 164 /* check if bus is not busy */ 165 if (!i2c_isr_set_cleared(base, 0, ISR_IBB)) 166 goto transfer_error_bus_busy; 167 168 /* start receive */ 169 writel(readl(&base->icr) & ~ICR_START, &base->icr); 170 writel(readl(&base->icr) & ~ICR_STOP, &base->icr); 171 if (msg->condition == I2C_COND_START) 172 writel(readl(&base->icr) | ICR_START, &base->icr); 173 if (msg->condition == I2C_COND_STOP) 174 writel(readl(&base->icr) | ICR_STOP, &base->icr); 175 if (msg->acknack == I2C_ACKNAK_SENDNAK) 176 writel(readl(&base->icr) | ICR_ACKNAK, &base->icr); 177 if (msg->acknack == I2C_ACKNAK_SENDACK) 178 writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr); 179 writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr); 180 writel(readl(&base->icr) | ICR_TB, &base->icr); 181 182 /* receive register full? */ 183 if (!i2c_isr_set_cleared(base, ISR_IRF, 0)) 184 goto transfer_error_receive_timeout; 185 186 msg->data = readl(&base->idbr); 187 188 /* clear 'receive empty' state */ 189 writel(readl(&base->isr) | ISR_IRF, &base->isr); 190 break; 191 default: 192 goto transfer_error_illegal_param; 193 } 194 195 return 0; 196 197 transfer_error_msg_empty: 198 debug("i2c_transfer: error: 'msg' is empty\n"); 199 ret = -1; 200 goto i2c_transfer_finish; 201 202 transfer_error_transmit_timeout: 203 debug("i2c_transfer: error: transmit timeout\n"); 204 ret = -2; 205 goto i2c_transfer_finish; 206 207 transfer_error_ack_missing: 208 debug("i2c_transfer: error: ACK missing\n"); 209 ret = -3; 210 goto i2c_transfer_finish; 211 212 transfer_error_receive_timeout: 213 debug("i2c_transfer: error: receive timeout\n"); 214 ret = -4; 215 goto i2c_transfer_finish; 216 217 transfer_error_illegal_param: 218 debug("i2c_transfer: error: illegal parameters\n"); 219 ret = -5; 220 goto i2c_transfer_finish; 221 222 transfer_error_bus_busy: 223 debug("i2c_transfer: error: bus is busy\n"); 224 ret = -6; 225 goto i2c_transfer_finish; 226 227 i2c_transfer_finish: 228 debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr)); 229 i2c_reset(base); 230 return ret; 231 } 232 233 static int __i2c_read(struct mv_i2c *base, uchar chip, u8 *addr, int alen, 234 uchar *buffer, int len) 235 { 236 struct mv_i2c_msg msg; 237 238 debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, " 239 "len=0x%02x)\n", chip, *addr, alen, len); 240 241 i2c_reset(base); 242 243 /* dummy chip address write */ 244 debug("i2c_read: dummy chip address write\n"); 245 msg.condition = I2C_COND_START; 246 msg.acknack = I2C_ACKNAK_WAITACK; 247 msg.direction = I2C_WRITE; 248 msg.data = (chip << 1); 249 msg.data &= 0xFE; 250 if (i2c_transfer(base, &msg)) 251 return -1; 252 253 /* 254 * send memory address bytes; 255 * alen defines how much bytes we have to send. 256 */ 257 while (--alen >= 0) { 258 debug("i2c_read: send address byte %02x (alen=%d)\n", 259 *addr, alen); 260 msg.condition = I2C_COND_NORMAL; 261 msg.acknack = I2C_ACKNAK_WAITACK; 262 msg.direction = I2C_WRITE; 263 msg.data = *(addr++); 264 if (i2c_transfer(base, &msg)) 265 return -1; 266 } 267 268 /* start read sequence */ 269 debug("i2c_read: start read sequence\n"); 270 msg.condition = I2C_COND_START; 271 msg.acknack = I2C_ACKNAK_WAITACK; 272 msg.direction = I2C_WRITE; 273 msg.data = (chip << 1); 274 msg.data |= 0x01; 275 if (i2c_transfer(base, &msg)) 276 return -1; 277 278 /* read bytes; send NACK at last byte */ 279 while (len--) { 280 if (len == 0) { 281 msg.condition = I2C_COND_STOP; 282 msg.acknack = I2C_ACKNAK_SENDNAK; 283 } else { 284 msg.condition = I2C_COND_NORMAL; 285 msg.acknack = I2C_ACKNAK_SENDACK; 286 } 287 288 msg.direction = I2C_READ; 289 msg.data = 0x00; 290 if (i2c_transfer(base, &msg)) 291 return -1; 292 293 *buffer = msg.data; 294 debug("i2c_read: reading byte (%p)=0x%02x\n", 295 buffer, *buffer); 296 buffer++; 297 } 298 299 i2c_reset(base); 300 301 return 0; 302 } 303 304 static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen, 305 uchar *buffer, int len) 306 { 307 struct mv_i2c_msg msg; 308 309 debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, " 310 "len=0x%02x)\n", chip, *addr, alen, len); 311 312 i2c_reset(base); 313 314 /* chip address write */ 315 debug("i2c_write: chip address write\n"); 316 msg.condition = I2C_COND_START; 317 msg.acknack = I2C_ACKNAK_WAITACK; 318 msg.direction = I2C_WRITE; 319 msg.data = (chip << 1); 320 msg.data &= 0xFE; 321 if (i2c_transfer(base, &msg)) 322 return -1; 323 324 /* 325 * send memory address bytes; 326 * alen defines how much bytes we have to send. 327 */ 328 while (--alen >= 0) { 329 debug("i2c_read: send address byte %02x (alen=%d)\n", 330 *addr, alen); 331 msg.condition = I2C_COND_NORMAL; 332 msg.acknack = I2C_ACKNAK_WAITACK; 333 msg.direction = I2C_WRITE; 334 msg.data = *(addr++); 335 if (i2c_transfer(base, &msg)) 336 return -1; 337 } 338 339 /* write bytes; send NACK at last byte */ 340 while (len--) { 341 debug("i2c_write: writing byte (%p)=0x%02x\n", 342 buffer, *buffer); 343 344 if (len == 0) 345 msg.condition = I2C_COND_STOP; 346 else 347 msg.condition = I2C_COND_NORMAL; 348 349 msg.acknack = I2C_ACKNAK_WAITACK; 350 msg.direction = I2C_WRITE; 351 msg.data = *(buffer++); 352 353 if (i2c_transfer(base, &msg)) 354 return -1; 355 } 356 357 i2c_reset(base); 358 359 return 0; 360 } 361 362 #ifndef CONFIG_DM_I2C 363 364 static struct mv_i2c *base_glob; 365 366 static void i2c_board_init(struct mv_i2c *base) 367 { 368 #ifdef CONFIG_SYS_I2C_INIT_BOARD 369 u32 icr; 370 /* 371 * call board specific i2c bus reset routine before accessing the 372 * environment, which might be in a chip on that bus. For details 373 * about this problem see doc/I2C_Edge_Conditions. 374 * 375 * disable I2C controller first, otherwhise it thinks we want to 376 * talk to the slave port... 377 */ 378 icr = readl(&base->icr); 379 writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr); 380 381 i2c_init_board(); 382 383 writel(icr, &base->icr); 384 #endif 385 } 386 387 #ifdef CONFIG_I2C_MULTI_BUS 388 static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG; 389 static unsigned int bus_initialized[CONFIG_MV_I2C_NUM]; 390 static unsigned int current_bus; 391 392 int i2c_set_bus_num(unsigned int bus) 393 { 394 if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) { 395 printf("Bad bus: %d\n", bus); 396 return -1; 397 } 398 399 base_glob = (struct mv_i2c *)i2c_regs[bus]; 400 current_bus = bus; 401 402 if (!bus_initialized[current_bus]) { 403 i2c_board_init(base_glob); 404 bus_initialized[current_bus] = 1; 405 } 406 407 return 0; 408 } 409 410 unsigned int i2c_get_bus_num(void) 411 { 412 return current_bus; 413 } 414 #endif 415 416 /* API Functions */ 417 void i2c_init(int speed, int slaveaddr) 418 { 419 #ifdef CONFIG_I2C_MULTI_BUS 420 current_bus = 0; 421 base_glob = (struct mv_i2c *)i2c_regs[current_bus]; 422 #else 423 base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG; 424 #endif 425 426 i2c_board_init(base_glob); 427 } 428 429 static int __i2c_probe_chip(struct mv_i2c *base, uchar chip) 430 { 431 struct mv_i2c_msg msg; 432 433 i2c_reset(base); 434 435 msg.condition = I2C_COND_START; 436 msg.acknack = I2C_ACKNAK_WAITACK; 437 msg.direction = I2C_WRITE; 438 msg.data = (chip << 1) + 1; 439 if (i2c_transfer(base, &msg)) 440 return -1; 441 442 msg.condition = I2C_COND_STOP; 443 msg.acknack = I2C_ACKNAK_SENDNAK; 444 msg.direction = I2C_READ; 445 msg.data = 0x00; 446 if (i2c_transfer(base, &msg)) 447 return -1; 448 449 return 0; 450 } 451 452 /* 453 * i2c_probe: - Test if a chip answers for a given i2c address 454 * 455 * @chip: address of the chip which is searched for 456 * @return: 0 if a chip was found, -1 otherwhise 457 */ 458 int i2c_probe(uchar chip) 459 { 460 return __i2c_probe_chip(base_glob, chip); 461 } 462 463 /* 464 * i2c_read: - Read multiple bytes from an i2c device 465 * 466 * The higher level routines take into account that this function is only 467 * called with len < page length of the device (see configuration file) 468 * 469 * @chip: address of the chip which is to be read 470 * @addr: i2c data address within the chip 471 * @alen: length of the i2c data address (1..2 bytes) 472 * @buffer: where to write the data 473 * @len: how much byte do we want to read 474 * @return: 0 in case of success 475 */ 476 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 477 { 478 u8 addr_bytes[4]; 479 480 addr_bytes[0] = (addr >> 0) & 0xFF; 481 addr_bytes[1] = (addr >> 8) & 0xFF; 482 addr_bytes[2] = (addr >> 16) & 0xFF; 483 addr_bytes[3] = (addr >> 24) & 0xFF; 484 485 return __i2c_read(base_glob, chip, addr_bytes, alen, buffer, len); 486 } 487 488 /* 489 * i2c_write: - Write multiple bytes to an i2c device 490 * 491 * The higher level routines take into account that this function is only 492 * called with len < page length of the device (see configuration file) 493 * 494 * @chip: address of the chip which is to be written 495 * @addr: i2c data address within the chip 496 * @alen: length of the i2c data address (1..2 bytes) 497 * @buffer: where to find the data to be written 498 * @len: how much byte do we want to read 499 * @return: 0 in case of success 500 */ 501 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 502 { 503 u8 addr_bytes[4]; 504 505 addr_bytes[0] = (addr >> 0) & 0xFF; 506 addr_bytes[1] = (addr >> 8) & 0xFF; 507 addr_bytes[2] = (addr >> 16) & 0xFF; 508 addr_bytes[3] = (addr >> 24) & 0xFF; 509 510 return __i2c_write(base_glob, chip, addr_bytes, alen, buffer, len); 511 } 512 513 #else /* CONFIG_DM_I2C */ 514 515 struct mv_i2c_priv { 516 struct mv_i2c *base; 517 }; 518 519 static int mv_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 520 { 521 struct mv_i2c_priv *i2c = dev_get_priv(bus); 522 struct i2c_msg *dmsg, *omsg, dummy; 523 524 memset(&dummy, 0, sizeof(struct i2c_msg)); 525 526 /* 527 * We expect either two messages (one with an offset and one with the 528 * actual data) or one message (just data or offset/data combined) 529 */ 530 if (nmsgs > 2 || nmsgs == 0) { 531 debug("%s: Only one or two messages are supported.", __func__); 532 return -1; 533 } 534 535 omsg = nmsgs == 1 ? &dummy : msg; 536 dmsg = nmsgs == 1 ? msg : msg + 1; 537 538 if (dmsg->flags & I2C_M_RD) 539 return __i2c_read(i2c->base, dmsg->addr, omsg->buf, 540 omsg->len, dmsg->buf, dmsg->len); 541 else 542 return __i2c_write(i2c->base, dmsg->addr, omsg->buf, 543 omsg->len, dmsg->buf, dmsg->len); 544 } 545 546 static int mv_i2c_probe(struct udevice *bus) 547 { 548 struct mv_i2c_priv *priv = dev_get_priv(bus); 549 550 priv->base = (void *)dev_get_addr_ptr(bus); 551 552 return 0; 553 } 554 555 static const struct dm_i2c_ops mv_i2c_ops = { 556 .xfer = mv_i2c_xfer, 557 }; 558 559 static const struct udevice_id mv_i2c_ids[] = { 560 { .compatible = "marvell,armada-3700-i2c" }, 561 { } 562 }; 563 564 U_BOOT_DRIVER(i2c_mv) = { 565 .name = "i2c_mv", 566 .id = UCLASS_I2C, 567 .of_match = mv_i2c_ids, 568 .probe = mv_i2c_probe, 569 .priv_auto_alloc_size = sizeof(struct mv_i2c_priv), 570 .ops = &mv_i2c_ops, 571 }; 572 #endif /* CONFIG_DM_I2C */ 573