168432c27SLei Wen /* 268432c27SLei Wen * (C) Copyright 2000 368432c27SLei Wen * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it 468432c27SLei Wen * 568432c27SLei Wen * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 668432c27SLei Wen * Marius Groeger <mgroeger@sysgo.de> 768432c27SLei Wen * 868432c27SLei Wen * (C) Copyright 2003 Pengutronix e.K. 968432c27SLei Wen * Robert Schwebel <r.schwebel@pengutronix.de> 1068432c27SLei Wen * 113df619ecSLei Wen * (C) Copyright 2011 Marvell Inc. 123df619ecSLei Wen * Lei Wen <leiwen@marvell.com> 133df619ecSLei Wen * 141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 1568432c27SLei Wen * 1668432c27SLei Wen * Back ported to the 8xx platform (from the 8260 platform) by 1768432c27SLei Wen * Murray.Jensen@cmst.csiro.au, 27-Jan-01. 1868432c27SLei Wen */ 1968432c27SLei Wen 2068432c27SLei Wen #include <common.h> 2168432c27SLei Wen #include <i2c.h> 22*7b46ee52SStefan Roese #include <asm/io.h> 233df619ecSLei Wen #include "mv_i2c.h" 2468432c27SLei Wen 2568432c27SLei Wen /* All transfers are described by this data structure */ 26fffff726SSimon Glass struct mv_i2c_msg { 2768432c27SLei Wen u8 condition; 2868432c27SLei Wen u8 acknack; 2968432c27SLei Wen u8 direction; 3068432c27SLei Wen u8 data; 3168432c27SLei Wen }; 3268432c27SLei Wen 333df619ecSLei Wen struct mv_i2c { 343df619ecSLei Wen u32 ibmr; 353df619ecSLei Wen u32 pad0; 363df619ecSLei Wen u32 idbr; 373df619ecSLei Wen u32 pad1; 383df619ecSLei Wen u32 icr; 393df619ecSLei Wen u32 pad2; 403df619ecSLei Wen u32 isr; 413df619ecSLei Wen u32 pad3; 423df619ecSLei Wen u32 isar; 433df619ecSLei Wen }; 443df619ecSLei Wen 4568432c27SLei Wen /* 463df619ecSLei Wen * i2c_reset: - reset the host controller 4768432c27SLei Wen * 4868432c27SLei Wen */ 49*7b46ee52SStefan Roese static void i2c_reset(struct mv_i2c *base) 5068432c27SLei Wen { 513df619ecSLei Wen writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ 523df619ecSLei Wen writel(readl(&base->icr) | ICR_UR, &base->icr); /* reset the unit */ 5368432c27SLei Wen udelay(100); 543df619ecSLei Wen writel(readl(&base->icr) & ~ICR_IUE, &base->icr); /* disable unit */ 553df619ecSLei Wen 563df619ecSLei Wen i2c_clk_enable(); 573df619ecSLei Wen 583df619ecSLei Wen writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ 593df619ecSLei Wen writel(I2C_ICR_INIT, &base->icr); /* set control reg values */ 603df619ecSLei Wen writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ 613df619ecSLei Wen writel(readl(&base->icr) | ICR_IUE, &base->icr); /* enable unit */ 6268432c27SLei Wen udelay(100); 6368432c27SLei Wen } 6468432c27SLei Wen 6568432c27SLei Wen /* 6668432c27SLei Wen * i2c_isr_set_cleared: - wait until certain bits of the I2C status register 6768432c27SLei Wen * are set and cleared 6868432c27SLei Wen * 6968432c27SLei Wen * @return: 1 in case of success, 0 means timeout (no match within 10 ms). 7068432c27SLei Wen */ 71*7b46ee52SStefan Roese static int i2c_isr_set_cleared(struct mv_i2c *base, unsigned long set_mask, 7268432c27SLei Wen unsigned long cleared_mask) 7368432c27SLei Wen { 743df619ecSLei Wen int timeout = 1000, isr; 7568432c27SLei Wen 763df619ecSLei Wen do { 773df619ecSLei Wen isr = readl(&base->isr); 7868432c27SLei Wen udelay(10); 7968432c27SLei Wen if (timeout-- < 0) 8068432c27SLei Wen return 0; 813df619ecSLei Wen } while (((isr & set_mask) != set_mask) 823df619ecSLei Wen || ((isr & cleared_mask) != 0)); 8368432c27SLei Wen 8468432c27SLei Wen return 1; 8568432c27SLei Wen } 8668432c27SLei Wen 8768432c27SLei Wen /* 8868432c27SLei Wen * i2c_transfer: - Transfer one byte over the i2c bus 8968432c27SLei Wen * 9068432c27SLei Wen * This function can tranfer a byte over the i2c bus in both directions. 9168432c27SLei Wen * It is used by the public API functions. 9268432c27SLei Wen * 9368432c27SLei Wen * @return: 0: transfer successful 9468432c27SLei Wen * -1: message is empty 9568432c27SLei Wen * -2: transmit timeout 9668432c27SLei Wen * -3: ACK missing 9768432c27SLei Wen * -4: receive timeout 9868432c27SLei Wen * -5: illegal parameters 9968432c27SLei Wen * -6: bus is busy and couldn't be aquired 10068432c27SLei Wen */ 101*7b46ee52SStefan Roese static int i2c_transfer(struct mv_i2c *base, struct mv_i2c_msg *msg) 10268432c27SLei Wen { 10368432c27SLei Wen int ret; 10468432c27SLei Wen 10568432c27SLei Wen if (!msg) 10668432c27SLei Wen goto transfer_error_msg_empty; 10768432c27SLei Wen 10868432c27SLei Wen switch (msg->direction) { 10968432c27SLei Wen case I2C_WRITE: 11068432c27SLei Wen /* check if bus is not busy */ 111*7b46ee52SStefan Roese if (!i2c_isr_set_cleared(base, 0, ISR_IBB)) 11268432c27SLei Wen goto transfer_error_bus_busy; 11368432c27SLei Wen 11468432c27SLei Wen /* start transmission */ 1153df619ecSLei Wen writel(readl(&base->icr) & ~ICR_START, &base->icr); 1163df619ecSLei Wen writel(readl(&base->icr) & ~ICR_STOP, &base->icr); 1173df619ecSLei Wen writel(msg->data, &base->idbr); 11868432c27SLei Wen if (msg->condition == I2C_COND_START) 1193df619ecSLei Wen writel(readl(&base->icr) | ICR_START, &base->icr); 12068432c27SLei Wen if (msg->condition == I2C_COND_STOP) 1213df619ecSLei Wen writel(readl(&base->icr) | ICR_STOP, &base->icr); 12268432c27SLei Wen if (msg->acknack == I2C_ACKNAK_SENDNAK) 1233df619ecSLei Wen writel(readl(&base->icr) | ICR_ACKNAK, &base->icr); 12468432c27SLei Wen if (msg->acknack == I2C_ACKNAK_SENDACK) 1253df619ecSLei Wen writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr); 1263df619ecSLei Wen writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr); 1273df619ecSLei Wen writel(readl(&base->icr) | ICR_TB, &base->icr); 12868432c27SLei Wen 12968432c27SLei Wen /* transmit register empty? */ 130*7b46ee52SStefan Roese if (!i2c_isr_set_cleared(base, ISR_ITE, 0)) 13168432c27SLei Wen goto transfer_error_transmit_timeout; 13268432c27SLei Wen 13368432c27SLei Wen /* clear 'transmit empty' state */ 1343df619ecSLei Wen writel(readl(&base->isr) | ISR_ITE, &base->isr); 13568432c27SLei Wen 13668432c27SLei Wen /* wait for ACK from slave */ 13768432c27SLei Wen if (msg->acknack == I2C_ACKNAK_WAITACK) 138*7b46ee52SStefan Roese if (!i2c_isr_set_cleared(base, 0, ISR_ACKNAK)) 13968432c27SLei Wen goto transfer_error_ack_missing; 14068432c27SLei Wen break; 14168432c27SLei Wen 14268432c27SLei Wen case I2C_READ: 14368432c27SLei Wen 14468432c27SLei Wen /* check if bus is not busy */ 145*7b46ee52SStefan Roese if (!i2c_isr_set_cleared(base, 0, ISR_IBB)) 14668432c27SLei Wen goto transfer_error_bus_busy; 14768432c27SLei Wen 14868432c27SLei Wen /* start receive */ 1493df619ecSLei Wen writel(readl(&base->icr) & ~ICR_START, &base->icr); 1503df619ecSLei Wen writel(readl(&base->icr) & ~ICR_STOP, &base->icr); 15168432c27SLei Wen if (msg->condition == I2C_COND_START) 1523df619ecSLei Wen writel(readl(&base->icr) | ICR_START, &base->icr); 15368432c27SLei Wen if (msg->condition == I2C_COND_STOP) 1543df619ecSLei Wen writel(readl(&base->icr) | ICR_STOP, &base->icr); 15568432c27SLei Wen if (msg->acknack == I2C_ACKNAK_SENDNAK) 1563df619ecSLei Wen writel(readl(&base->icr) | ICR_ACKNAK, &base->icr); 15768432c27SLei Wen if (msg->acknack == I2C_ACKNAK_SENDACK) 1583df619ecSLei Wen writel(readl(&base->icr) & ~ICR_ACKNAK, &base->icr); 1593df619ecSLei Wen writel(readl(&base->icr) & ~ICR_ALDIE, &base->icr); 1603df619ecSLei Wen writel(readl(&base->icr) | ICR_TB, &base->icr); 16168432c27SLei Wen 16268432c27SLei Wen /* receive register full? */ 163*7b46ee52SStefan Roese if (!i2c_isr_set_cleared(base, ISR_IRF, 0)) 16468432c27SLei Wen goto transfer_error_receive_timeout; 16568432c27SLei Wen 1663df619ecSLei Wen msg->data = readl(&base->idbr); 16768432c27SLei Wen 16868432c27SLei Wen /* clear 'receive empty' state */ 1693df619ecSLei Wen writel(readl(&base->isr) | ISR_IRF, &base->isr); 17068432c27SLei Wen break; 17168432c27SLei Wen default: 17268432c27SLei Wen goto transfer_error_illegal_param; 17368432c27SLei Wen } 17468432c27SLei Wen 17568432c27SLei Wen return 0; 17668432c27SLei Wen 17768432c27SLei Wen transfer_error_msg_empty: 1788eff909aSStefan Roese debug("i2c_transfer: error: 'msg' is empty\n"); 1798eff909aSStefan Roese ret = -1; 1808eff909aSStefan Roese goto i2c_transfer_finish; 18168432c27SLei Wen 18268432c27SLei Wen transfer_error_transmit_timeout: 1838eff909aSStefan Roese debug("i2c_transfer: error: transmit timeout\n"); 1848eff909aSStefan Roese ret = -2; 1858eff909aSStefan Roese goto i2c_transfer_finish; 18668432c27SLei Wen 18768432c27SLei Wen transfer_error_ack_missing: 1888eff909aSStefan Roese debug("i2c_transfer: error: ACK missing\n"); 1898eff909aSStefan Roese ret = -3; 1908eff909aSStefan Roese goto i2c_transfer_finish; 19168432c27SLei Wen 19268432c27SLei Wen transfer_error_receive_timeout: 1938eff909aSStefan Roese debug("i2c_transfer: error: receive timeout\n"); 1948eff909aSStefan Roese ret = -4; 1958eff909aSStefan Roese goto i2c_transfer_finish; 19668432c27SLei Wen 19768432c27SLei Wen transfer_error_illegal_param: 1988eff909aSStefan Roese debug("i2c_transfer: error: illegal parameters\n"); 1998eff909aSStefan Roese ret = -5; 2008eff909aSStefan Roese goto i2c_transfer_finish; 20168432c27SLei Wen 20268432c27SLei Wen transfer_error_bus_busy: 2038eff909aSStefan Roese debug("i2c_transfer: error: bus is busy\n"); 2048eff909aSStefan Roese ret = -6; 2058eff909aSStefan Roese goto i2c_transfer_finish; 20668432c27SLei Wen 20768432c27SLei Wen i2c_transfer_finish: 2088eff909aSStefan Roese debug("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr)); 209*7b46ee52SStefan Roese i2c_reset(base); 21068432c27SLei Wen return ret; 21168432c27SLei Wen } 21268432c27SLei Wen 213*7b46ee52SStefan Roese static int __i2c_probe_chip(struct mv_i2c *base, uchar chip) 21468432c27SLei Wen { 215fffff726SSimon Glass struct mv_i2c_msg msg; 21668432c27SLei Wen 217*7b46ee52SStefan Roese i2c_reset(base); 21868432c27SLei Wen 21968432c27SLei Wen msg.condition = I2C_COND_START; 22068432c27SLei Wen msg.acknack = I2C_ACKNAK_WAITACK; 22168432c27SLei Wen msg.direction = I2C_WRITE; 22268432c27SLei Wen msg.data = (chip << 1) + 1; 223*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 22468432c27SLei Wen return -1; 22568432c27SLei Wen 22668432c27SLei Wen msg.condition = I2C_COND_STOP; 22768432c27SLei Wen msg.acknack = I2C_ACKNAK_SENDNAK; 22868432c27SLei Wen msg.direction = I2C_READ; 22968432c27SLei Wen msg.data = 0x00; 230*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 23168432c27SLei Wen return -1; 23268432c27SLei Wen 23368432c27SLei Wen return 0; 23468432c27SLei Wen } 23568432c27SLei Wen 236*7b46ee52SStefan Roese static int __i2c_read(struct mv_i2c *base, uchar chip, uint addr, int alen, 237*7b46ee52SStefan Roese uchar *buffer, int len) 23868432c27SLei Wen { 239fffff726SSimon Glass struct mv_i2c_msg msg; 24068432c27SLei Wen u8 addr_bytes[3]; /* lowest...highest byte of data address */ 24168432c27SLei Wen 2428eff909aSStefan Roese debug("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, " 2438eff909aSStefan Roese "len=0x%02x)\n", chip, addr, alen, len); 24468432c27SLei Wen 245*7b46ee52SStefan Roese i2c_reset(base); 24668432c27SLei Wen 24768432c27SLei Wen /* dummy chip address write */ 2488eff909aSStefan Roese debug("i2c_read: dummy chip address write\n"); 24968432c27SLei Wen msg.condition = I2C_COND_START; 25068432c27SLei Wen msg.acknack = I2C_ACKNAK_WAITACK; 25168432c27SLei Wen msg.direction = I2C_WRITE; 25268432c27SLei Wen msg.data = (chip << 1); 25368432c27SLei Wen msg.data &= 0xFE; 254*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 25568432c27SLei Wen return -1; 25668432c27SLei Wen 25768432c27SLei Wen /* 25868432c27SLei Wen * send memory address bytes; 25968432c27SLei Wen * alen defines how much bytes we have to send. 26068432c27SLei Wen */ 26168432c27SLei Wen /*addr &= ((1 << CONFIG_SYS_EEPROM_PAGE_WRITE_BITS)-1); */ 26268432c27SLei Wen addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); 26368432c27SLei Wen addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); 26468432c27SLei Wen addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); 26568432c27SLei Wen 26668432c27SLei Wen while (--alen >= 0) { 2678eff909aSStefan Roese debug("i2c_read: send memory word address byte %1d\n", alen); 26868432c27SLei Wen msg.condition = I2C_COND_NORMAL; 26968432c27SLei Wen msg.acknack = I2C_ACKNAK_WAITACK; 27068432c27SLei Wen msg.direction = I2C_WRITE; 27168432c27SLei Wen msg.data = addr_bytes[alen]; 272*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 27368432c27SLei Wen return -1; 27468432c27SLei Wen } 27568432c27SLei Wen 27668432c27SLei Wen /* start read sequence */ 2778eff909aSStefan Roese debug("i2c_read: start read sequence\n"); 27868432c27SLei Wen msg.condition = I2C_COND_START; 27968432c27SLei Wen msg.acknack = I2C_ACKNAK_WAITACK; 28068432c27SLei Wen msg.direction = I2C_WRITE; 28168432c27SLei Wen msg.data = (chip << 1); 28268432c27SLei Wen msg.data |= 0x01; 283*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 28468432c27SLei Wen return -1; 28568432c27SLei Wen 28668432c27SLei Wen /* read bytes; send NACK at last byte */ 28768432c27SLei Wen while (len--) { 28868432c27SLei Wen if (len == 0) { 28968432c27SLei Wen msg.condition = I2C_COND_STOP; 29068432c27SLei Wen msg.acknack = I2C_ACKNAK_SENDNAK; 29168432c27SLei Wen } else { 29268432c27SLei Wen msg.condition = I2C_COND_NORMAL; 29368432c27SLei Wen msg.acknack = I2C_ACKNAK_SENDACK; 29468432c27SLei Wen } 29568432c27SLei Wen 29668432c27SLei Wen msg.direction = I2C_READ; 29768432c27SLei Wen msg.data = 0x00; 298*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 29968432c27SLei Wen return -1; 30068432c27SLei Wen 30168432c27SLei Wen *buffer = msg.data; 3028eff909aSStefan Roese debug("i2c_read: reading byte (0x%08x)=0x%02x\n", 3038eff909aSStefan Roese (unsigned int)buffer, *buffer); 30468432c27SLei Wen buffer++; 30568432c27SLei Wen } 30668432c27SLei Wen 307*7b46ee52SStefan Roese i2c_reset(base); 30868432c27SLei Wen 30968432c27SLei Wen return 0; 31068432c27SLei Wen } 31168432c27SLei Wen 312*7b46ee52SStefan Roese static int __i2c_write(struct mv_i2c *base, uchar chip, uint addr, int alen, 313*7b46ee52SStefan Roese uchar *buffer, int len) 31468432c27SLei Wen { 315fffff726SSimon Glass struct mv_i2c_msg msg; 31668432c27SLei Wen u8 addr_bytes[3]; /* lowest...highest byte of data address */ 31768432c27SLei Wen 3188eff909aSStefan Roese debug("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, " 3198eff909aSStefan Roese "len=0x%02x)\n", chip, addr, alen, len); 32068432c27SLei Wen 321*7b46ee52SStefan Roese i2c_reset(base); 32268432c27SLei Wen 32368432c27SLei Wen /* chip address write */ 3248eff909aSStefan Roese debug("i2c_write: chip address write\n"); 32568432c27SLei Wen msg.condition = I2C_COND_START; 32668432c27SLei Wen msg.acknack = I2C_ACKNAK_WAITACK; 32768432c27SLei Wen msg.direction = I2C_WRITE; 32868432c27SLei Wen msg.data = (chip << 1); 32968432c27SLei Wen msg.data &= 0xFE; 330*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 33168432c27SLei Wen return -1; 33268432c27SLei Wen 33368432c27SLei Wen /* 33468432c27SLei Wen * send memory address bytes; 33568432c27SLei Wen * alen defines how much bytes we have to send. 33668432c27SLei Wen */ 33768432c27SLei Wen addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); 33868432c27SLei Wen addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); 33968432c27SLei Wen addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); 34068432c27SLei Wen 34168432c27SLei Wen while (--alen >= 0) { 3428eff909aSStefan Roese debug("i2c_write: send memory word address\n"); 34368432c27SLei Wen msg.condition = I2C_COND_NORMAL; 34468432c27SLei Wen msg.acknack = I2C_ACKNAK_WAITACK; 34568432c27SLei Wen msg.direction = I2C_WRITE; 34668432c27SLei Wen msg.data = addr_bytes[alen]; 347*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 34868432c27SLei Wen return -1; 34968432c27SLei Wen } 35068432c27SLei Wen 35168432c27SLei Wen /* write bytes; send NACK at last byte */ 35268432c27SLei Wen while (len--) { 3538eff909aSStefan Roese debug("i2c_write: writing byte (0x%08x)=0x%02x\n", 3548eff909aSStefan Roese (unsigned int)buffer, *buffer); 35568432c27SLei Wen 35668432c27SLei Wen if (len == 0) 35768432c27SLei Wen msg.condition = I2C_COND_STOP; 35868432c27SLei Wen else 35968432c27SLei Wen msg.condition = I2C_COND_NORMAL; 36068432c27SLei Wen 36168432c27SLei Wen msg.acknack = I2C_ACKNAK_WAITACK; 36268432c27SLei Wen msg.direction = I2C_WRITE; 36368432c27SLei Wen msg.data = *(buffer++); 36468432c27SLei Wen 365*7b46ee52SStefan Roese if (i2c_transfer(base, &msg)) 36668432c27SLei Wen return -1; 36768432c27SLei Wen } 36868432c27SLei Wen 369*7b46ee52SStefan Roese i2c_reset(base); 37068432c27SLei Wen 37168432c27SLei Wen return 0; 37268432c27SLei Wen } 373*7b46ee52SStefan Roese 374*7b46ee52SStefan Roese static struct mv_i2c *base_glob; 375*7b46ee52SStefan Roese 376*7b46ee52SStefan Roese static void i2c_board_init(struct mv_i2c *base) 377*7b46ee52SStefan Roese { 378*7b46ee52SStefan Roese #ifdef CONFIG_SYS_I2C_INIT_BOARD 379*7b46ee52SStefan Roese u32 icr; 380*7b46ee52SStefan Roese /* 381*7b46ee52SStefan Roese * call board specific i2c bus reset routine before accessing the 382*7b46ee52SStefan Roese * environment, which might be in a chip on that bus. For details 383*7b46ee52SStefan Roese * about this problem see doc/I2C_Edge_Conditions. 384*7b46ee52SStefan Roese * 385*7b46ee52SStefan Roese * disable I2C controller first, otherwhise it thinks we want to 386*7b46ee52SStefan Roese * talk to the slave port... 387*7b46ee52SStefan Roese */ 388*7b46ee52SStefan Roese icr = readl(&base->icr); 389*7b46ee52SStefan Roese writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr); 390*7b46ee52SStefan Roese 391*7b46ee52SStefan Roese i2c_init_board(); 392*7b46ee52SStefan Roese 393*7b46ee52SStefan Roese writel(icr, &base->icr); 394*7b46ee52SStefan Roese #endif 395*7b46ee52SStefan Roese } 396*7b46ee52SStefan Roese 397*7b46ee52SStefan Roese #ifdef CONFIG_I2C_MULTI_BUS 398*7b46ee52SStefan Roese static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG; 399*7b46ee52SStefan Roese static unsigned int bus_initialized[CONFIG_MV_I2C_NUM]; 400*7b46ee52SStefan Roese static unsigned int current_bus; 401*7b46ee52SStefan Roese 402*7b46ee52SStefan Roese int i2c_set_bus_num(unsigned int bus) 403*7b46ee52SStefan Roese { 404*7b46ee52SStefan Roese if ((bus < 0) || (bus >= CONFIG_MV_I2C_NUM)) { 405*7b46ee52SStefan Roese printf("Bad bus: %d\n", bus); 406*7b46ee52SStefan Roese return -1; 407*7b46ee52SStefan Roese } 408*7b46ee52SStefan Roese 409*7b46ee52SStefan Roese base_glob = (struct mv_i2c *)i2c_regs[bus]; 410*7b46ee52SStefan Roese current_bus = bus; 411*7b46ee52SStefan Roese 412*7b46ee52SStefan Roese if (!bus_initialized[current_bus]) { 413*7b46ee52SStefan Roese i2c_board_init(base_glob); 414*7b46ee52SStefan Roese bus_initialized[current_bus] = 1; 415*7b46ee52SStefan Roese } 416*7b46ee52SStefan Roese 417*7b46ee52SStefan Roese return 0; 418*7b46ee52SStefan Roese } 419*7b46ee52SStefan Roese 420*7b46ee52SStefan Roese unsigned int i2c_get_bus_num(void) 421*7b46ee52SStefan Roese { 422*7b46ee52SStefan Roese return current_bus; 423*7b46ee52SStefan Roese } 424*7b46ee52SStefan Roese #endif 425*7b46ee52SStefan Roese 426*7b46ee52SStefan Roese /* API Functions */ 427*7b46ee52SStefan Roese void i2c_init(int speed, int slaveaddr) 428*7b46ee52SStefan Roese { 429*7b46ee52SStefan Roese #ifdef CONFIG_I2C_MULTI_BUS 430*7b46ee52SStefan Roese current_bus = 0; 431*7b46ee52SStefan Roese base_glob = (struct mv_i2c *)i2c_regs[current_bus]; 432*7b46ee52SStefan Roese #else 433*7b46ee52SStefan Roese base_glob = (struct mv_i2c *)CONFIG_MV_I2C_REG; 434*7b46ee52SStefan Roese #endif 435*7b46ee52SStefan Roese 436*7b46ee52SStefan Roese i2c_board_init(base_glob); 437*7b46ee52SStefan Roese } 438*7b46ee52SStefan Roese 439*7b46ee52SStefan Roese /* 440*7b46ee52SStefan Roese * i2c_probe: - Test if a chip answers for a given i2c address 441*7b46ee52SStefan Roese * 442*7b46ee52SStefan Roese * @chip: address of the chip which is searched for 443*7b46ee52SStefan Roese * @return: 0 if a chip was found, -1 otherwhise 444*7b46ee52SStefan Roese */ 445*7b46ee52SStefan Roese int i2c_probe(uchar chip) 446*7b46ee52SStefan Roese { 447*7b46ee52SStefan Roese return __i2c_probe_chip(base_glob, chip); 448*7b46ee52SStefan Roese } 449*7b46ee52SStefan Roese 450*7b46ee52SStefan Roese /* 451*7b46ee52SStefan Roese * i2c_read: - Read multiple bytes from an i2c device 452*7b46ee52SStefan Roese * 453*7b46ee52SStefan Roese * The higher level routines take into account that this function is only 454*7b46ee52SStefan Roese * called with len < page length of the device (see configuration file) 455*7b46ee52SStefan Roese * 456*7b46ee52SStefan Roese * @chip: address of the chip which is to be read 457*7b46ee52SStefan Roese * @addr: i2c data address within the chip 458*7b46ee52SStefan Roese * @alen: length of the i2c data address (1..2 bytes) 459*7b46ee52SStefan Roese * @buffer: where to write the data 460*7b46ee52SStefan Roese * @len: how much byte do we want to read 461*7b46ee52SStefan Roese * @return: 0 in case of success 462*7b46ee52SStefan Roese */ 463*7b46ee52SStefan Roese int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 464*7b46ee52SStefan Roese { 465*7b46ee52SStefan Roese return __i2c_read(base_glob, chip, addr, alen, buffer, len); 466*7b46ee52SStefan Roese } 467*7b46ee52SStefan Roese 468*7b46ee52SStefan Roese /* 469*7b46ee52SStefan Roese * i2c_write: - Write multiple bytes to an i2c device 470*7b46ee52SStefan Roese * 471*7b46ee52SStefan Roese * The higher level routines take into account that this function is only 472*7b46ee52SStefan Roese * called with len < page length of the device (see configuration file) 473*7b46ee52SStefan Roese * 474*7b46ee52SStefan Roese * @chip: address of the chip which is to be written 475*7b46ee52SStefan Roese * @addr: i2c data address within the chip 476*7b46ee52SStefan Roese * @alen: length of the i2c data address (1..2 bytes) 477*7b46ee52SStefan Roese * @buffer: where to find the data to be written 478*7b46ee52SStefan Roese * @len: how much byte do we want to read 479*7b46ee52SStefan Roese * @return: 0 in case of success 480*7b46ee52SStefan Roese */ 481*7b46ee52SStefan Roese int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 482*7b46ee52SStefan Roese { 483*7b46ee52SStefan Roese return __i2c_write(base_glob, chip, addr, alen, buffer, len); 484*7b46ee52SStefan Roese } 485