1abb0b01eSSimon Glass /* 2abb0b01eSSimon Glass * Copyright (c) 2015 Google, Inc 3abb0b01eSSimon Glass * Written by Simon Glass <sjg@chromium.org> 4abb0b01eSSimon Glass * 5abb0b01eSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 6abb0b01eSSimon Glass */ 7abb0b01eSSimon Glass 8abb0b01eSSimon Glass #include <common.h> 9abb0b01eSSimon Glass #include <dm.h> 10abb0b01eSSimon Glass #include <i2c.h> 11abb0b01eSSimon Glass #include <asm/io.h> 12*0c7645bdSSimon Glass #include <asm/arch/pch.h> 13abb0b01eSSimon Glass 14abb0b01eSSimon Glass int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 15abb0b01eSSimon Glass { 16abb0b01eSSimon Glass return -ENOSYS; 17abb0b01eSSimon Glass } 18abb0b01eSSimon Glass 19abb0b01eSSimon Glass int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags) 20abb0b01eSSimon Glass { 21abb0b01eSSimon Glass return -ENOSYS; 22abb0b01eSSimon Glass } 23abb0b01eSSimon Glass 24abb0b01eSSimon Glass int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 25abb0b01eSSimon Glass { 26abb0b01eSSimon Glass return 0; 27abb0b01eSSimon Glass } 28abb0b01eSSimon Glass 29abb0b01eSSimon Glass static int intel_i2c_probe(struct udevice *dev) 30abb0b01eSSimon Glass { 31*0c7645bdSSimon Glass /* 32*0c7645bdSSimon Glass * So far this is just setup code for ivybridge SMbus. When we have 33*0c7645bdSSimon Glass * a full I2C driver this may need to be moved, generalised or made 34*0c7645bdSSimon Glass * dependant on a particular compatible string. 35*0c7645bdSSimon Glass * 36*0c7645bdSSimon Glass * Set SMBus I/O base 37*0c7645bdSSimon Glass */ 38*0c7645bdSSimon Glass dm_pci_write_config32(dev, SMB_BASE, 39*0c7645bdSSimon Glass SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); 40*0c7645bdSSimon Glass 41*0c7645bdSSimon Glass /* Set SMBus enable. */ 42*0c7645bdSSimon Glass dm_pci_write_config8(dev, HOSTC, HST_EN); 43*0c7645bdSSimon Glass 44*0c7645bdSSimon Glass /* Set SMBus I/O space enable. */ 45*0c7645bdSSimon Glass dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); 46*0c7645bdSSimon Glass 47*0c7645bdSSimon Glass /* Disable interrupt generation. */ 48*0c7645bdSSimon Glass outb(0, SMBUS_IO_BASE + SMBHSTCTL); 49*0c7645bdSSimon Glass 50*0c7645bdSSimon Glass /* Clear any lingering errors, so transactions can run. */ 51*0c7645bdSSimon Glass outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); 52*0c7645bdSSimon Glass debug("SMBus controller enabled\n"); 53*0c7645bdSSimon Glass 54abb0b01eSSimon Glass return 0; 55abb0b01eSSimon Glass } 56abb0b01eSSimon Glass 57abb0b01eSSimon Glass static const struct dm_i2c_ops intel_i2c_ops = { 58abb0b01eSSimon Glass .xfer = intel_i2c_xfer, 59abb0b01eSSimon Glass .probe_chip = intel_i2c_probe_chip, 60abb0b01eSSimon Glass .set_bus_speed = intel_i2c_set_bus_speed, 61abb0b01eSSimon Glass }; 62abb0b01eSSimon Glass 63abb0b01eSSimon Glass static const struct udevice_id intel_i2c_ids[] = { 64abb0b01eSSimon Glass { .compatible = "intel,ich-i2c" }, 65abb0b01eSSimon Glass { } 66abb0b01eSSimon Glass }; 67abb0b01eSSimon Glass 68abb0b01eSSimon Glass U_BOOT_DRIVER(intel_i2c) = { 69abb0b01eSSimon Glass .name = "i2c_intel", 70abb0b01eSSimon Glass .id = UCLASS_I2C, 71abb0b01eSSimon Glass .of_match = intel_i2c_ids, 72abb0b01eSSimon Glass .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), 73abb0b01eSSimon Glass .ops = &intel_i2c_ops, 74abb0b01eSSimon Glass .probe = intel_i2c_probe, 75abb0b01eSSimon Glass }; 76