1 /* 2 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com> 3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) 4 * 5 * This file is based on: drivers/i2c/zynq_i2c.c, 6 * with added driver-model support and code cleanup. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <linux/types.h> 13 #include <linux/io.h> 14 #include <asm/errno.h> 15 #include <dm/device.h> 16 #include <dm/root.h> 17 #include <i2c.h> 18 #include <fdtdec.h> 19 #include <mapmem.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* i2c register set */ 24 struct cdns_i2c_regs { 25 u32 control; 26 u32 status; 27 u32 address; 28 u32 data; 29 u32 interrupt_status; 30 u32 transfer_size; 31 u32 slave_mon_pause; 32 u32 time_out; 33 u32 interrupt_mask; 34 u32 interrupt_enable; 35 u32 interrupt_disable; 36 }; 37 38 /* Control register fields */ 39 #define CDNS_I2C_CONTROL_RW 0x00000001 40 #define CDNS_I2C_CONTROL_MS 0x00000002 41 #define CDNS_I2C_CONTROL_NEA 0x00000004 42 #define CDNS_I2C_CONTROL_ACKEN 0x00000008 43 #define CDNS_I2C_CONTROL_HOLD 0x00000010 44 #define CDNS_I2C_CONTROL_SLVMON 0x00000020 45 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 47 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 49 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 50 51 /* Status register values */ 52 #define CDNS_I2C_STATUS_RXDV 0x00000020 53 #define CDNS_I2C_STATUS_TXDV 0x00000040 54 #define CDNS_I2C_STATUS_RXOVF 0x00000080 55 #define CDNS_I2C_STATUS_BA 0x00000100 56 57 /* Interrupt register fields */ 58 #define CDNS_I2C_INTERRUPT_COMP 0x00000001 59 #define CDNS_I2C_INTERRUPT_DATA 0x00000002 60 #define CDNS_I2C_INTERRUPT_NACK 0x00000004 61 #define CDNS_I2C_INTERRUPT_TO 0x00000008 62 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 63 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 64 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 65 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 66 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 67 68 #define CDNS_I2C_FIFO_DEPTH 16 69 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ 70 71 #ifdef DEBUG 72 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) 73 { 74 int int_status; 75 int status; 76 int_status = readl(&cdns_i2c->interrupt_status); 77 78 status = readl(&cdns_i2c->status); 79 if (int_status || status) { 80 debug("Status: "); 81 if (int_status & CDNS_I2C_INTERRUPT_COMP) 82 debug("COMP "); 83 if (int_status & CDNS_I2C_INTERRUPT_DATA) 84 debug("DATA "); 85 if (int_status & CDNS_I2C_INTERRUPT_NACK) 86 debug("NACK "); 87 if (int_status & CDNS_I2C_INTERRUPT_TO) 88 debug("TO "); 89 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) 90 debug("SLVRDY "); 91 if (int_status & CDNS_I2C_INTERRUPT_RXOVF) 92 debug("RXOVF "); 93 if (int_status & CDNS_I2C_INTERRUPT_TXOVF) 94 debug("TXOVF "); 95 if (int_status & CDNS_I2C_INTERRUPT_RXUNF) 96 debug("RXUNF "); 97 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) 98 debug("ARBLOST "); 99 if (status & CDNS_I2C_STATUS_RXDV) 100 debug("RXDV "); 101 if (status & CDNS_I2C_STATUS_TXDV) 102 debug("TXDV "); 103 if (status & CDNS_I2C_STATUS_RXOVF) 104 debug("RXOVF "); 105 if (status & CDNS_I2C_STATUS_BA) 106 debug("BA "); 107 debug("TS%d ", readl(&cdns_i2c->transfer_size)); 108 debug("\n"); 109 } 110 } 111 #endif 112 113 struct i2c_cdns_bus { 114 int id; 115 struct cdns_i2c_regs __iomem *regs; /* register base */ 116 }; 117 118 119 /** cdns_i2c_probe() - Probe method 120 * @dev: udevice pointer 121 * 122 * DM callback called when device is probed 123 */ 124 static int cdns_i2c_probe(struct udevice *dev) 125 { 126 struct i2c_cdns_bus *bus = dev_get_priv(dev); 127 128 /* TODO: Calculate dividers based on CPU_CLK_1X */ 129 /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ 130 writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) | 131 (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); 132 133 /* Enable master mode, ack, and 7-bit addressing */ 134 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | 135 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); 136 137 debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); 138 139 return 0; 140 } 141 142 static int cdns_i2c_remove(struct udevice *dev) 143 { 144 struct i2c_cdns_bus *bus = dev_get_priv(dev); 145 146 debug("%s bus %d at %p\n", __func__, dev->seq, bus->regs); 147 148 unmap_sysmem(bus->regs); 149 150 return 0; 151 } 152 153 /* Wait for an interrupt */ 154 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) 155 { 156 int timeout, int_status; 157 158 for (timeout = 0; timeout < 100; timeout++) { 159 udelay(100); 160 int_status = readl(&cdns_i2c->interrupt_status); 161 if (int_status & mask) 162 break; 163 } 164 165 /* Clear interrupt status flags */ 166 writel(int_status & mask, &cdns_i2c->interrupt_status); 167 168 return int_status & mask; 169 } 170 171 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 172 { 173 if (speed != 100000) { 174 printf("%s, failed to set clock speed to %u\n", __func__, 175 speed); 176 return -EINVAL; 177 } 178 179 return 0; 180 } 181 182 /* Probe to see if a chip is present. */ 183 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, 184 uint chip_flags) 185 { 186 struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus); 187 struct cdns_i2c_regs *regs = i2c_bus->regs; 188 189 /* Attempt to read a byte */ 190 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 191 CDNS_I2C_CONTROL_RW); 192 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 193 writel(0xFF, ®s->interrupt_status); 194 writel(chip_addr, ®s->address); 195 writel(1, ®s->transfer_size); 196 197 return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 198 CDNS_I2C_INTERRUPT_NACK) & 199 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; 200 } 201 202 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 203 u32 len, bool next_is_read) 204 { 205 u8 *cur_data = data; 206 207 struct cdns_i2c_regs *regs = i2c_bus->regs; 208 209 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 210 CDNS_I2C_CONTROL_HOLD); 211 212 /* if next is a read, we need to clear HOLD, doesn't work */ 213 if (next_is_read) 214 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 215 216 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); 217 218 writel(0xFF, ®s->interrupt_status); 219 writel(addr, ®s->address); 220 221 while (len--) { 222 writel(*(cur_data++), ®s->data); 223 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { 224 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) { 225 /* Release the bus */ 226 clrbits_le32(®s->control, 227 CDNS_I2C_CONTROL_HOLD); 228 return -ETIMEDOUT; 229 } 230 } 231 } 232 233 /* All done... release the bus */ 234 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 235 /* Wait for the address and data to be sent */ 236 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) 237 return -ETIMEDOUT; 238 return 0; 239 } 240 241 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 242 u32 len) 243 { 244 u32 status; 245 u32 i = 0; 246 u8 *cur_data = data; 247 248 /* TODO: Fix this */ 249 struct cdns_i2c_regs *regs = i2c_bus->regs; 250 251 /* Check the hardware can handle the requested bytes */ 252 if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX)) 253 return -EINVAL; 254 255 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 256 CDNS_I2C_CONTROL_RW); 257 258 /* Start reading data */ 259 writel(addr, ®s->address); 260 writel(len, ®s->transfer_size); 261 262 /* Wait for data */ 263 do { 264 status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 265 CDNS_I2C_INTERRUPT_DATA); 266 if (!status) { 267 /* Release the bus */ 268 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 269 return -ETIMEDOUT; 270 } 271 debug("Read %d bytes\n", 272 len - readl(®s->transfer_size)); 273 for (; i < len - readl(®s->transfer_size); i++) 274 *(cur_data++) = readl(®s->data); 275 } while (readl(®s->transfer_size) != 0); 276 /* All done... release the bus */ 277 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 278 279 #ifdef DEBUG 280 cdns_i2c_debug_status(regs); 281 #endif 282 return 0; 283 } 284 285 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 286 int nmsgs) 287 { 288 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 289 int ret; 290 291 debug("i2c_xfer: %d messages\n", nmsgs); 292 for (; nmsgs > 0; nmsgs--, msg++) { 293 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 294 295 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 296 if (msg->flags & I2C_M_RD) { 297 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, 298 msg->len); 299 } else { 300 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, 301 msg->len, next_is_read); 302 } 303 if (ret) { 304 debug("i2c_write: error sending\n"); 305 return -EREMOTEIO; 306 } 307 } 308 309 return 0; 310 } 311 312 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) 313 { 314 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 315 316 i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); 317 if (!i2c_bus->regs) 318 return -ENOMEM; 319 320 return 0; 321 } 322 323 static const struct dm_i2c_ops cdns_i2c_ops = { 324 .xfer = cdns_i2c_xfer, 325 .probe_chip = cdns_i2c_probe_chip, 326 .set_bus_speed = cdns_i2c_set_bus_speed, 327 }; 328 329 static const struct udevice_id cdns_i2c_of_match[] = { 330 { .compatible = "cdns,i2c-r1p10" }, 331 { /* end of table */ } 332 }; 333 334 U_BOOT_DRIVER(cdns_i2c) = { 335 .name = "i2c-cdns", 336 .id = UCLASS_I2C, 337 .of_match = cdns_i2c_of_match, 338 .probe = cdns_i2c_probe, 339 .remove = cdns_i2c_remove, 340 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata, 341 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), 342 .ops = &cdns_i2c_ops, 343 }; 344