1 /* 2 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com> 3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2) 4 * 5 * This file is based on: drivers/i2c/zynq_i2c.c, 6 * with added driver-model support and code cleanup. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <linux/types.h> 13 #include <linux/io.h> 14 #include <linux/errno.h> 15 #include <dm/device.h> 16 #include <dm/root.h> 17 #include <i2c.h> 18 #include <fdtdec.h> 19 #include <mapmem.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* i2c register set */ 24 struct cdns_i2c_regs { 25 u32 control; 26 u32 status; 27 u32 address; 28 u32 data; 29 u32 interrupt_status; 30 u32 transfer_size; 31 u32 slave_mon_pause; 32 u32 time_out; 33 u32 interrupt_mask; 34 u32 interrupt_enable; 35 u32 interrupt_disable; 36 }; 37 38 /* Control register fields */ 39 #define CDNS_I2C_CONTROL_RW 0x00000001 40 #define CDNS_I2C_CONTROL_MS 0x00000002 41 #define CDNS_I2C_CONTROL_NEA 0x00000004 42 #define CDNS_I2C_CONTROL_ACKEN 0x00000008 43 #define CDNS_I2C_CONTROL_HOLD 0x00000010 44 #define CDNS_I2C_CONTROL_SLVMON 0x00000020 45 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040 46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8 47 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00 48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14 49 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000 50 51 /* Status register values */ 52 #define CDNS_I2C_STATUS_RXDV 0x00000020 53 #define CDNS_I2C_STATUS_TXDV 0x00000040 54 #define CDNS_I2C_STATUS_RXOVF 0x00000080 55 #define CDNS_I2C_STATUS_BA 0x00000100 56 57 /* Interrupt register fields */ 58 #define CDNS_I2C_INTERRUPT_COMP 0x00000001 59 #define CDNS_I2C_INTERRUPT_DATA 0x00000002 60 #define CDNS_I2C_INTERRUPT_NACK 0x00000004 61 #define CDNS_I2C_INTERRUPT_TO 0x00000008 62 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010 63 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020 64 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040 65 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080 66 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200 67 68 #define CDNS_I2C_FIFO_DEPTH 16 69 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */ 70 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0) 71 72 #ifdef DEBUG 73 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c) 74 { 75 int int_status; 76 int status; 77 int_status = readl(&cdns_i2c->interrupt_status); 78 79 status = readl(&cdns_i2c->status); 80 if (int_status || status) { 81 debug("Status: "); 82 if (int_status & CDNS_I2C_INTERRUPT_COMP) 83 debug("COMP "); 84 if (int_status & CDNS_I2C_INTERRUPT_DATA) 85 debug("DATA "); 86 if (int_status & CDNS_I2C_INTERRUPT_NACK) 87 debug("NACK "); 88 if (int_status & CDNS_I2C_INTERRUPT_TO) 89 debug("TO "); 90 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY) 91 debug("SLVRDY "); 92 if (int_status & CDNS_I2C_INTERRUPT_RXOVF) 93 debug("RXOVF "); 94 if (int_status & CDNS_I2C_INTERRUPT_TXOVF) 95 debug("TXOVF "); 96 if (int_status & CDNS_I2C_INTERRUPT_RXUNF) 97 debug("RXUNF "); 98 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST) 99 debug("ARBLOST "); 100 if (status & CDNS_I2C_STATUS_RXDV) 101 debug("RXDV "); 102 if (status & CDNS_I2C_STATUS_TXDV) 103 debug("TXDV "); 104 if (status & CDNS_I2C_STATUS_RXOVF) 105 debug("RXOVF "); 106 if (status & CDNS_I2C_STATUS_BA) 107 debug("BA "); 108 debug("TS%d ", readl(&cdns_i2c->transfer_size)); 109 debug("\n"); 110 } 111 } 112 #endif 113 114 struct i2c_cdns_bus { 115 int id; 116 unsigned int input_freq; 117 struct cdns_i2c_regs __iomem *regs; /* register base */ 118 119 int hold_flag; 120 u32 quirks; 121 }; 122 123 struct cdns_i2c_platform_data { 124 u32 quirks; 125 }; 126 127 /* Wait for an interrupt */ 128 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask) 129 { 130 int timeout, int_status; 131 132 for (timeout = 0; timeout < 100; timeout++) { 133 int_status = readl(&cdns_i2c->interrupt_status); 134 if (int_status & mask) 135 break; 136 udelay(100); 137 } 138 139 /* Clear interrupt status flags */ 140 writel(int_status & mask, &cdns_i2c->interrupt_status); 141 142 return int_status & mask; 143 } 144 145 #define CDNS_I2C_DIVA_MAX 4 146 #define CDNS_I2C_DIVB_MAX 64 147 148 static int cdns_i2c_calc_divs(unsigned long *f, unsigned long input_clk, 149 unsigned int *a, unsigned int *b) 150 { 151 unsigned long fscl = *f, best_fscl = *f, actual_fscl, temp; 152 unsigned int div_a, div_b, calc_div_a = 0, calc_div_b = 0; 153 unsigned int last_error, current_error; 154 155 /* calculate (divisor_a+1) x (divisor_b+1) */ 156 temp = input_clk / (22 * fscl); 157 158 /* 159 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX, 160 * the fscl input is out of range. Return error. 161 */ 162 if (!temp || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) 163 return -EINVAL; 164 165 last_error = -1; 166 for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) { 167 div_b = DIV_ROUND_UP(input_clk, 22 * fscl * (div_a + 1)); 168 169 if ((div_b < 1) || (div_b > CDNS_I2C_DIVB_MAX)) 170 continue; 171 div_b--; 172 173 actual_fscl = input_clk / (22 * (div_a + 1) * (div_b + 1)); 174 175 if (actual_fscl > fscl) 176 continue; 177 178 current_error = ((actual_fscl > fscl) ? (actual_fscl - fscl) : 179 (fscl - actual_fscl)); 180 181 if (last_error > current_error) { 182 calc_div_a = div_a; 183 calc_div_b = div_b; 184 best_fscl = actual_fscl; 185 last_error = current_error; 186 } 187 } 188 189 *a = calc_div_a; 190 *b = calc_div_b; 191 *f = best_fscl; 192 193 return 0; 194 } 195 196 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 197 { 198 struct i2c_cdns_bus *bus = dev_get_priv(dev); 199 u32 div_a = 0, div_b = 0; 200 unsigned long speed_p = speed; 201 int ret = 0; 202 203 if (speed > 400000) { 204 debug("%s, failed to set clock speed to %u\n", __func__, 205 speed); 206 return -EINVAL; 207 } 208 209 ret = cdns_i2c_calc_divs(&speed_p, bus->input_freq, &div_a, &div_b); 210 if (ret) 211 return ret; 212 213 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n", 214 __func__, div_a, div_b, bus->input_freq, speed, speed_p); 215 216 writel((div_b << CDNS_I2C_CONTROL_DIV_B_SHIFT) | 217 (div_a << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control); 218 219 /* Enable master mode, ack, and 7-bit addressing */ 220 setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS | 221 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA); 222 223 return 0; 224 } 225 226 /* Probe to see if a chip is present. */ 227 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr, 228 uint chip_flags) 229 { 230 struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus); 231 struct cdns_i2c_regs *regs = i2c_bus->regs; 232 233 /* Attempt to read a byte */ 234 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 235 CDNS_I2C_CONTROL_RW); 236 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 237 writel(0xFF, ®s->interrupt_status); 238 writel(chip_addr, ®s->address); 239 writel(1, ®s->transfer_size); 240 241 return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 242 CDNS_I2C_INTERRUPT_NACK) & 243 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; 244 } 245 246 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 247 u32 len) 248 { 249 u8 *cur_data = data; 250 251 struct cdns_i2c_regs *regs = i2c_bus->regs; 252 253 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO); 254 255 256 clrbits_le32(®s->control, CDNS_I2C_CONTROL_RW); 257 258 writel(0xFF, ®s->interrupt_status); 259 writel(addr, ®s->address); 260 261 while (len--) { 262 writel(*(cur_data++), ®s->data); 263 if (readl(®s->transfer_size) == CDNS_I2C_FIFO_DEPTH) { 264 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) { 265 /* Release the bus */ 266 clrbits_le32(®s->control, 267 CDNS_I2C_CONTROL_HOLD); 268 return -ETIMEDOUT; 269 } 270 } 271 } 272 273 /* All done... release the bus */ 274 if (!i2c_bus->hold_flag) 275 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 276 277 /* Wait for the address and data to be sent */ 278 if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) 279 return -ETIMEDOUT; 280 return 0; 281 } 282 283 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data, 284 u32 len) 285 { 286 u32 status; 287 u32 i = 0; 288 u8 *cur_data = data; 289 290 /* TODO: Fix this */ 291 struct cdns_i2c_regs *regs = i2c_bus->regs; 292 293 /* Check the hardware can handle the requested bytes */ 294 if ((len < 0)) 295 return -EINVAL; 296 297 setbits_le32(®s->control, CDNS_I2C_CONTROL_CLR_FIFO | 298 CDNS_I2C_CONTROL_RW); 299 300 /* Start reading data */ 301 writel(addr, ®s->address); 302 writel(len, ®s->transfer_size); 303 304 /* Wait for data */ 305 do { 306 status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP | 307 CDNS_I2C_INTERRUPT_DATA); 308 if (!status) { 309 /* Release the bus */ 310 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 311 return -ETIMEDOUT; 312 } 313 debug("Read %d bytes\n", 314 len - readl(®s->transfer_size)); 315 for (; i < len - readl(®s->transfer_size); i++) 316 *(cur_data++) = readl(®s->data); 317 } while (readl(®s->transfer_size) != 0); 318 /* All done... release the bus */ 319 if (!i2c_bus->hold_flag) 320 clrbits_le32(®s->control, CDNS_I2C_CONTROL_HOLD); 321 322 #ifdef DEBUG 323 cdns_i2c_debug_status(regs); 324 #endif 325 return 0; 326 } 327 328 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, 329 int nmsgs) 330 { 331 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 332 int ret, count; 333 bool hold_quirk; 334 335 hold_quirk = !!(i2c_bus->quirks & CDNS_I2C_BROKEN_HOLD_BIT); 336 337 if (nmsgs > 1) { 338 /* 339 * This controller does not give completion interrupt after a 340 * master receive message if HOLD bit is set (repeated start), 341 * resulting in SW timeout. Hence, if a receive message is 342 * followed by any other message, an error is returned 343 * indicating that this sequence is not supported. 344 */ 345 for (count = 0; (count < nmsgs - 1) && hold_quirk; count++) { 346 if (msg[count].flags & I2C_M_RD) { 347 printf("Can't do repeated start after a receive message\n"); 348 return -EOPNOTSUPP; 349 } 350 } 351 352 i2c_bus->hold_flag = 1; 353 setbits_le32(&i2c_bus->regs->control, CDNS_I2C_CONTROL_HOLD); 354 } else { 355 i2c_bus->hold_flag = 0; 356 } 357 358 debug("i2c_xfer: %d messages\n", nmsgs); 359 for (; nmsgs > 0; nmsgs--, msg++) { 360 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 361 if (msg->flags & I2C_M_RD) { 362 ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf, 363 msg->len); 364 } else { 365 ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf, 366 msg->len); 367 } 368 if (ret) { 369 debug("i2c_write: error sending\n"); 370 return -EREMOTEIO; 371 } 372 } 373 374 return 0; 375 } 376 377 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) 378 { 379 struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); 380 struct cdns_i2c_platform_data *pdata = 381 (struct cdns_i2c_platform_data *)dev_get_driver_data(dev); 382 383 i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev); 384 if (!i2c_bus->regs) 385 return -ENOMEM; 386 387 if (pdata) 388 i2c_bus->quirks = pdata->quirks; 389 390 i2c_bus->input_freq = 100000000; /* TODO hardcode input freq for now */ 391 392 return 0; 393 } 394 395 static const struct dm_i2c_ops cdns_i2c_ops = { 396 .xfer = cdns_i2c_xfer, 397 .probe_chip = cdns_i2c_probe_chip, 398 .set_bus_speed = cdns_i2c_set_bus_speed, 399 }; 400 401 static const struct cdns_i2c_platform_data r1p10_i2c_def = { 402 .quirks = CDNS_I2C_BROKEN_HOLD_BIT, 403 }; 404 405 static const struct udevice_id cdns_i2c_of_match[] = { 406 { .compatible = "cdns,i2c-r1p10", .data = (ulong)&r1p10_i2c_def }, 407 { .compatible = "cdns,i2c-r1p14" }, 408 { /* end of table */ } 409 }; 410 411 U_BOOT_DRIVER(cdns_i2c) = { 412 .name = "i2c-cdns", 413 .id = UCLASS_I2C, 414 .of_match = cdns_i2c_of_match, 415 .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata, 416 .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus), 417 .ops = &cdns_i2c_ops, 418 }; 419