1 /* 2 * Faraday I2C Controller 3 * 4 * (C) Copyright 2010 Faraday Technology 5 * Dante Su <dantesu@faraday-tech.com> 6 * 7 * This file is released under the terms of GPL v2 and any later version. 8 * See the file COPYING in the root directory of the source tree for details. 9 */ 10 11 #ifndef __FTI2C010_H 12 #define __FTI2C010_H 13 14 /* 15 * FTI2C010 registers 16 */ 17 struct fti2c010_regs { 18 uint32_t cr; /* 0x00: control register */ 19 uint32_t sr; /* 0x04: status register */ 20 uint32_t cdr; /* 0x08: clock division register */ 21 uint32_t dr; /* 0x0c: data register */ 22 uint32_t sar; /* 0x10: slave address register */ 23 uint32_t tgsr;/* 0x14: time & glitch suppression register */ 24 uint32_t bmr; /* 0x18: bus monitor register */ 25 uint32_t rsvd[5]; 26 uint32_t revr;/* 0x30: revision register */ 27 }; 28 29 /* 30 * control register 31 */ 32 #define CR_ALIRQ 0x2000 /* arbitration lost interrupt (master) */ 33 #define CR_SAMIRQ 0x1000 /* slave address match interrupt (slave) */ 34 #define CR_STOPIRQ 0x800 /* stop condition interrupt (slave) */ 35 #define CR_NAKRIRQ 0x400 /* NACK response interrupt (master) */ 36 #define CR_DRIRQ 0x200 /* rx interrupt (both) */ 37 #define CR_DTIRQ 0x100 /* tx interrupt (both) */ 38 #define CR_TBEN 0x80 /* tx enable (both) */ 39 #define CR_NAK 0x40 /* NACK (both) */ 40 #define CR_STOP 0x20 /* stop (master) */ 41 #define CR_START 0x10 /* start (master) */ 42 #define CR_GCEN 0x8 /* general call support (slave) */ 43 #define CR_SCLEN 0x4 /* enable clock out (master) */ 44 #define CR_I2CEN 0x2 /* enable I2C (both) */ 45 #define CR_I2CRST 0x1 /* reset I2C (both) */ 46 #define CR_ENABLE \ 47 (CR_ALIRQ | CR_NAKRIRQ | CR_DRIRQ | CR_DTIRQ | CR_SCLEN | CR_I2CEN) 48 49 /* 50 * status register 51 */ 52 #define SR_CLRAL 0x400 /* clear arbitration lost */ 53 #define SR_CLRGC 0x200 /* clear general call */ 54 #define SR_CLRSAM 0x100 /* clear slave address match */ 55 #define SR_CLRSTOP 0x80 /* clear stop */ 56 #define SR_CLRNAKR 0x40 /* clear NACK respond */ 57 #define SR_DR 0x20 /* rx ready */ 58 #define SR_DT 0x10 /* tx done */ 59 #define SR_BB 0x8 /* bus busy */ 60 #define SR_BUSY 0x4 /* chip busy */ 61 #define SR_ACK 0x2 /* ACK/NACK received */ 62 #define SR_RW 0x1 /* set when master-rx or slave-tx mode */ 63 64 /* 65 * clock division register 66 */ 67 #define CDR_DIV(n) ((n) & 0x3ffff) 68 69 /* 70 * time & glitch suppression register 71 */ 72 #define TGSR_GSR(n) (((n) & 0x7) << 10) 73 #define TGSR_TSR(n) ((n) & 0x3ff) 74 75 /* 76 * bus monitor register 77 */ 78 #define BMR_SCL 0x2 /* SCL is pull-up */ 79 #define BMR_SDA 0x1 /* SDA is pull-up */ 80 81 #endif /* __FTI2C010_H */ 82