1 /* 2 * Copyright 2006,2009 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 /* The maximum number of microseconds we will wait until another master has 30 * released the bus. If not defined in the board header file, then use a 31 * generic value. 32 */ 33 #ifndef CONFIG_I2C_MBB_TIMEOUT 34 #define CONFIG_I2C_MBB_TIMEOUT 100000 35 #endif 36 37 /* The maximum number of microseconds we will wait for a read or write 38 * operation to complete. If not defined in the board header file, then use a 39 * generic value. 40 */ 41 #ifndef CONFIG_I2C_TIMEOUT 42 #define CONFIG_I2C_TIMEOUT 10000 43 #endif 44 45 #define I2C_READ_BIT 1 46 #define I2C_WRITE_BIT 0 47 48 DECLARE_GLOBAL_DATA_PTR; 49 50 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 51 * Default is bus 0. This is necessary because the DDR initialization 52 * runs from ROM, and we can't switch buses because we can't modify 53 * the global variables. 54 */ 55 #ifndef CONFIG_SYS_SPD_BUS_NUM 56 #define CONFIG_SYS_SPD_BUS_NUM 0 57 #endif 58 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; 59 #if defined(CONFIG_I2C_MUX) 60 static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; 61 #endif 62 63 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; 64 65 static const struct fsl_i2c *i2c_dev[2] = { 66 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), 67 #ifdef CONFIG_SYS_I2C2_OFFSET 68 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) 69 #endif 70 }; 71 72 /* I2C speed map for a DFSR value of 1 */ 73 74 /* 75 * Map I2C frequency dividers to FDR and DFSR values 76 * 77 * This structure is used to define the elements of a table that maps I2C 78 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 79 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 80 * Sampling Rate (DFSR) registers. 81 * 82 * The actual table should be defined in the board file, and it must be called 83 * fsl_i2c_speed_map[]. 84 * 85 * The last entry of the table must have a value of {-1, X}, where X is same 86 * FDR/DFSR values as the second-to-last entry. This guarantees that any 87 * search through the array will always find a match. 88 * 89 * The values of the divider must be in increasing numerical order, i.e. 90 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 91 * 92 * For this table, the values are based on a value of 1 for the DFSR 93 * register. See the application note AN2919 "Determining the I2C Frequency 94 * Divider Ratio for SCL" 95 * 96 * ColdFire I2C frequency dividers for FDR values are different from 97 * PowerPC. The protocol to use the I2C module is still the same. 98 * A different table is defined and are based on MCF5xxx user manual. 99 * 100 */ 101 static const struct { 102 unsigned short divider; 103 #ifdef __PPC__ 104 u8 dfsr; 105 #endif 106 u8 fdr; 107 } fsl_i2c_speed_map[] = { 108 #ifdef __PPC__ 109 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, 110 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, 111 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, 112 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, 113 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, 114 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, 115 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, 116 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, 117 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, 118 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, 119 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, 120 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, 121 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, 122 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, 123 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, 124 {61440, 1, 31}, {-1, 1, 31} 125 #elif defined(__M68K__) 126 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 127 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 128 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 129 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 130 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 131 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 132 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 133 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 134 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 135 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 136 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 137 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 138 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 139 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 140 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 141 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 142 {-1, 31} 143 #endif 144 }; 145 146 /** 147 * Set the I2C bus speed for a given I2C device 148 * 149 * @param dev: the I2C device 150 * @i2c_clk: I2C bus clock frequency 151 * @speed: the desired speed of the bus 152 * 153 * The I2C device must be stopped before calling this function. 154 * 155 * The return value is the actual bus speed that is set. 156 */ 157 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 158 unsigned int i2c_clk, unsigned int speed) 159 { 160 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 161 unsigned int i; 162 163 /* 164 * We want to choose an FDR/DFSR that generates an I2C bus speed that 165 * is equal to or lower than the requested speed. That means that we 166 * want the first divider that is equal to or greater than the 167 * calculated divider. 168 */ 169 170 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 171 if (fsl_i2c_speed_map[i].divider >= divider) { 172 u8 fdr; 173 #ifdef __PPC__ 174 u8 dfsr; 175 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR 176 dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; 177 #else 178 dfsr = fsl_i2c_speed_map[i].dfsr; 179 #endif 180 writeb(dfsr, &dev->dfsrr); /* set default filter */ 181 #endif 182 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR 183 fdr = CONFIG_FSL_I2C_CUSTOM_FDR; 184 speed = i2c_clk / divider; /* Fake something */ 185 #else 186 fdr = fsl_i2c_speed_map[i].fdr; 187 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 188 #endif 189 writeb(fdr, &dev->fdr); /* set bus speed */ 190 191 break; 192 } 193 194 return speed; 195 } 196 197 void 198 i2c_init(int speed, int slaveadd) 199 { 200 struct fsl_i2c *dev; 201 unsigned int temp; 202 203 #ifdef CONFIG_SYS_I2C_INIT_BOARD 204 /* call board specific i2c bus reset routine before accessing the */ 205 /* environment, which might be in a chip on that bus. For details */ 206 /* about this problem see doc/I2C_Edge_Conditions. */ 207 i2c_init_board(); 208 #endif 209 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); 210 211 writeb(0, &dev->cr); /* stop I2C controller */ 212 udelay(5); /* let it shutdown in peace */ 213 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 214 if (gd->flags & GD_FLG_RELOC) 215 i2c_bus_speed[0] = temp; 216 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 217 writeb(0x0, &dev->sr); /* clear status register */ 218 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 219 220 #ifdef CONFIG_SYS_I2C2_OFFSET 221 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); 222 223 writeb(0, &dev->cr); /* stop I2C controller */ 224 udelay(5); /* let it shutdown in peace */ 225 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 226 if (gd->flags & GD_FLG_RELOC) 227 i2c_bus_speed[1] = temp; 228 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 229 writeb(0x0, &dev->sr); /* clear status register */ 230 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 231 #endif 232 } 233 234 static int 235 i2c_wait4bus(void) 236 { 237 unsigned long long timeval = get_ticks(); 238 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); 239 240 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 241 if ((get_ticks() - timeval) > timeout) 242 return -1; 243 } 244 245 return 0; 246 } 247 248 static __inline__ int 249 i2c_wait(int write) 250 { 251 u32 csr; 252 unsigned long long timeval = get_ticks(); 253 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); 254 255 do { 256 csr = readb(&i2c_dev[i2c_bus_num]->sr); 257 if (!(csr & I2C_SR_MIF)) 258 continue; 259 /* Read again to allow register to stabilise */ 260 csr = readb(&i2c_dev[i2c_bus_num]->sr); 261 262 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 263 264 if (csr & I2C_SR_MAL) { 265 debug("i2c_wait: MAL\n"); 266 return -1; 267 } 268 269 if (!(csr & I2C_SR_MCF)) { 270 debug("i2c_wait: unfinished\n"); 271 return -1; 272 } 273 274 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 275 debug("i2c_wait: No RXACK\n"); 276 return -1; 277 } 278 279 return 0; 280 } while ((get_ticks() - timeval) < timeout); 281 282 debug("i2c_wait: timed out\n"); 283 return -1; 284 } 285 286 static __inline__ int 287 i2c_write_addr (u8 dev, u8 dir, int rsta) 288 { 289 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 290 | (rsta ? I2C_CR_RSTA : 0), 291 &i2c_dev[i2c_bus_num]->cr); 292 293 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 294 295 if (i2c_wait(I2C_WRITE_BIT) < 0) 296 return 0; 297 298 return 1; 299 } 300 301 static __inline__ int 302 __i2c_write(u8 *data, int length) 303 { 304 int i; 305 306 for (i = 0; i < length; i++) { 307 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 308 309 if (i2c_wait(I2C_WRITE_BIT) < 0) 310 break; 311 } 312 313 return i; 314 } 315 316 static __inline__ int 317 __i2c_read(u8 *data, int length) 318 { 319 int i; 320 321 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 322 &i2c_dev[i2c_bus_num]->cr); 323 324 /* dummy read */ 325 readb(&i2c_dev[i2c_bus_num]->dr); 326 327 for (i = 0; i < length; i++) { 328 if (i2c_wait(I2C_READ_BIT) < 0) 329 break; 330 331 /* Generate ack on last next to last byte */ 332 if (i == length - 2) 333 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 334 &i2c_dev[i2c_bus_num]->cr); 335 336 /* Generate stop on last byte */ 337 if (i == length - 1) 338 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); 339 340 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 341 } 342 343 return i; 344 } 345 346 int 347 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 348 { 349 int i = -1; /* signal error */ 350 u8 *a = (u8*)&addr; 351 352 if (i2c_wait4bus() >= 0 353 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 354 && __i2c_write(&a[4 - alen], alen) == alen) 355 i = 0; /* No error so far */ 356 357 if (length 358 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 359 i = __i2c_read(data, length); 360 361 if (length && i2c_wait4bus()) /* Wait until STOP */ 362 debug("i2c_read: wait4bus timed out\n"); 363 364 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 365 366 if (i == length) 367 return 0; 368 369 return -1; 370 } 371 372 int 373 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 374 { 375 int i = -1; /* signal error */ 376 u8 *a = (u8*)&addr; 377 378 if (i2c_wait4bus() >= 0 379 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 380 && __i2c_write(&a[4 - alen], alen) == alen) { 381 i = __i2c_write(data, length); 382 } 383 384 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 385 if (i2c_wait4bus()) /* Wait until STOP */ 386 debug("i2c_write: wait4bus timed out\n"); 387 388 if (i == length) 389 return 0; 390 391 return -1; 392 } 393 394 int 395 i2c_probe(uchar chip) 396 { 397 /* For unknow reason the controller will ACK when 398 * probing for a slave with the same address, so skip 399 * it. 400 */ 401 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 402 return -1; 403 404 return i2c_read(chip, 0, 0, NULL, 0); 405 } 406 407 int i2c_set_bus_num(unsigned int bus) 408 { 409 #if defined(CONFIG_I2C_MUX) 410 if (bus < CONFIG_SYS_MAX_I2C_BUS) { 411 i2c_bus_num = bus; 412 } else { 413 int ret; 414 415 ret = i2x_mux_select_mux(bus); 416 if (ret) 417 return ret; 418 i2c_bus_num = 0; 419 } 420 i2c_bus_num_mux = bus; 421 #else 422 #ifdef CONFIG_SYS_I2C2_OFFSET 423 if (bus > 1) { 424 #else 425 if (bus > 0) { 426 #endif 427 return -1; 428 } 429 430 i2c_bus_num = bus; 431 #endif 432 return 0; 433 } 434 435 int i2c_set_bus_speed(unsigned int speed) 436 { 437 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 438 439 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 440 i2c_bus_speed[i2c_bus_num] = 441 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 442 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 443 444 return 0; 445 } 446 447 unsigned int i2c_get_bus_num(void) 448 { 449 #if defined(CONFIG_I2C_MUX) 450 return i2c_bus_num_mux; 451 #else 452 return i2c_bus_num; 453 #endif 454 } 455 456 unsigned int i2c_get_bus_speed(void) 457 { 458 return i2c_bus_speed[i2c_bus_num]; 459 } 460 461 #endif /* CONFIG_HARD_I2C */ 462