1 /* 2 * Copyright 2006,2009 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * Version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 */ 18 19 #include <common.h> 20 21 #ifdef CONFIG_HARD_I2C 22 23 #include <command.h> 24 #include <i2c.h> /* Functional interface */ 25 26 #include <asm/io.h> 27 #include <asm/fsl_i2c.h> /* HW definitions */ 28 29 /* The maximum number of microseconds we will wait until another master has 30 * released the bus. If not defined in the board header file, then use a 31 * generic value. 32 */ 33 #ifndef CONFIG_I2C_MBB_TIMEOUT 34 #define CONFIG_I2C_MBB_TIMEOUT 100000 35 #endif 36 37 /* The maximum number of microseconds we will wait for a read or write 38 * operation to complete. If not defined in the board header file, then use a 39 * generic value. 40 */ 41 #ifndef CONFIG_I2C_TIMEOUT 42 #define CONFIG_I2C_TIMEOUT 10000 43 #endif 44 45 #define I2C_READ_BIT 1 46 #define I2C_WRITE_BIT 0 47 48 DECLARE_GLOBAL_DATA_PTR; 49 50 /* Initialize the bus pointer to whatever one the SPD EEPROM is on. 51 * Default is bus 0. This is necessary because the DDR initialization 52 * runs from ROM, and we can't switch buses because we can't modify 53 * the global variables. 54 */ 55 #ifndef CONFIG_SYS_SPD_BUS_NUM 56 #define CONFIG_SYS_SPD_BUS_NUM 0 57 #endif 58 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM; 59 #if defined(CONFIG_I2C_MUX) 60 static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; 61 #endif 62 63 static unsigned int i2c_bus_speed[2] = {CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SPEED}; 64 65 static const struct fsl_i2c *i2c_dev[2] = { 66 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET), 67 #ifdef CONFIG_SYS_I2C2_OFFSET 68 (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET) 69 #endif 70 }; 71 72 /* I2C speed map for a DFSR value of 1 */ 73 74 /* 75 * Map I2C frequency dividers to FDR and DFSR values 76 * 77 * This structure is used to define the elements of a table that maps I2C 78 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be 79 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter 80 * Sampling Rate (DFSR) registers. 81 * 82 * The actual table should be defined in the board file, and it must be called 83 * fsl_i2c_speed_map[]. 84 * 85 * The last entry of the table must have a value of {-1, X}, where X is same 86 * FDR/DFSR values as the second-to-last entry. This guarantees that any 87 * search through the array will always find a match. 88 * 89 * The values of the divider must be in increasing numerical order, i.e. 90 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. 91 * 92 * For this table, the values are based on a value of 1 for the DFSR 93 * register. See the application note AN2919 "Determining the I2C Frequency 94 * Divider Ratio for SCL" 95 * 96 * ColdFire I2C frequency dividers for FDR values are different from 97 * PowerPC. The protocol to use the I2C module is still the same. 98 * A different table is defined and are based on MCF5xxx user manual. 99 * 100 */ 101 static const struct { 102 unsigned short divider; 103 #ifdef __PPC__ 104 u8 dfsr; 105 #endif 106 u8 fdr; 107 } fsl_i2c_speed_map[] = { 108 #ifdef __PPC__ 109 {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, 110 {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, 111 {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, 112 {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, 113 {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, 114 {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, 115 {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, 116 {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, 117 {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, 118 {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, 119 {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, 120 {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, 121 {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, 122 {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, 123 {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, 124 {61440, 1, 31}, {-1, 1, 31} 125 #elif defined(__M68K__) 126 {20, 32}, {22, 33}, {24, 34}, {26, 35}, 127 {28, 0}, {28, 36}, {30, 1}, {32, 37}, 128 {34, 2}, {36, 38}, {40, 3}, {40, 39}, 129 {44, 4}, {48, 5}, {48, 40}, {56, 6}, 130 {56, 41}, {64, 42}, {68, 7}, {72, 43}, 131 {80, 8}, {80, 44}, {88, 9}, {96, 41}, 132 {104, 10}, {112, 42}, {128, 11}, {128, 43}, 133 {144, 12}, {160, 13}, {160, 48}, {192, 14}, 134 {192, 49}, {224, 50}, {240, 15}, {256, 51}, 135 {288, 16}, {320, 17}, {320, 52}, {384, 18}, 136 {384, 53}, {448, 54}, {480, 19}, {512, 55}, 137 {576, 20}, {640, 21}, {640, 56}, {768, 22}, 138 {768, 57}, {960, 23}, {896, 58}, {1024, 59}, 139 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, 140 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, 141 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, 142 {-1, 31} 143 #endif 144 }; 145 146 /** 147 * Set the I2C bus speed for a given I2C device 148 * 149 * @param dev: the I2C device 150 * @i2c_clk: I2C bus clock frequency 151 * @speed: the desired speed of the bus 152 * 153 * The I2C device must be stopped before calling this function. 154 * 155 * The return value is the actual bus speed that is set. 156 */ 157 static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, 158 unsigned int i2c_clk, unsigned int speed) 159 { 160 unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); 161 unsigned int i; 162 163 /* 164 * We want to choose an FDR/DFSR that generates an I2C bus speed that 165 * is equal to or lower than the requested speed. That means that we 166 * want the first divider that is equal to or greater than the 167 * calculated divider. 168 */ 169 170 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) 171 if (fsl_i2c_speed_map[i].divider >= divider) { 172 u8 fdr; 173 #ifdef __PPC__ 174 u8 dfsr; 175 dfsr = fsl_i2c_speed_map[i].dfsr; 176 #endif 177 fdr = fsl_i2c_speed_map[i].fdr; 178 speed = i2c_clk / fsl_i2c_speed_map[i].divider; 179 writeb(fdr, &dev->fdr); /* set bus speed */ 180 #ifdef __PPC__ 181 writeb(dfsr, &dev->dfsrr); /* set default filter */ 182 #endif 183 break; 184 } 185 186 return speed; 187 } 188 189 void 190 i2c_init(int speed, int slaveadd) 191 { 192 struct fsl_i2c *dev; 193 unsigned int temp; 194 195 #ifdef CONFIG_SYS_I2C_INIT_BOARD 196 /* call board specific i2c bus reset routine before accessing the */ 197 /* environment, which might be in a chip on that bus. For details */ 198 /* about this problem see doc/I2C_Edge_Conditions. */ 199 i2c_init_board(); 200 #endif 201 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); 202 203 writeb(0, &dev->cr); /* stop I2C controller */ 204 udelay(5); /* let it shutdown in peace */ 205 temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); 206 if (gd->flags & GD_FLG_RELOC) 207 i2c_bus_speed[0] = temp; 208 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 209 writeb(0x0, &dev->sr); /* clear status register */ 210 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 211 212 #ifdef CONFIG_SYS_I2C2_OFFSET 213 dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); 214 215 writeb(0, &dev->cr); /* stop I2C controller */ 216 udelay(5); /* let it shutdown in peace */ 217 temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); 218 if (gd->flags & GD_FLG_RELOC) 219 i2c_bus_speed[1] = temp; 220 writeb(slaveadd << 1, &dev->adr); /* write slave address */ 221 writeb(0x0, &dev->sr); /* clear status register */ 222 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ 223 #endif 224 } 225 226 static int 227 i2c_wait4bus(void) 228 { 229 unsigned long long timeval = get_ticks(); 230 const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); 231 232 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) { 233 if ((get_ticks() - timeval) > timeout) 234 return -1; 235 } 236 237 return 0; 238 } 239 240 static __inline__ int 241 i2c_wait(int write) 242 { 243 u32 csr; 244 unsigned long long timeval = get_ticks(); 245 const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT); 246 247 do { 248 csr = readb(&i2c_dev[i2c_bus_num]->sr); 249 if (!(csr & I2C_SR_MIF)) 250 continue; 251 /* Read again to allow register to stabilise */ 252 csr = readb(&i2c_dev[i2c_bus_num]->sr); 253 254 writeb(0x0, &i2c_dev[i2c_bus_num]->sr); 255 256 if (csr & I2C_SR_MAL) { 257 debug("i2c_wait: MAL\n"); 258 return -1; 259 } 260 261 if (!(csr & I2C_SR_MCF)) { 262 debug("i2c_wait: unfinished\n"); 263 return -1; 264 } 265 266 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { 267 debug("i2c_wait: No RXACK\n"); 268 return -1; 269 } 270 271 return 0; 272 } while ((get_ticks() - timeval) < timeout); 273 274 debug("i2c_wait: timed out\n"); 275 return -1; 276 } 277 278 static __inline__ int 279 i2c_write_addr (u8 dev, u8 dir, int rsta) 280 { 281 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX 282 | (rsta ? I2C_CR_RSTA : 0), 283 &i2c_dev[i2c_bus_num]->cr); 284 285 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr); 286 287 if (i2c_wait(I2C_WRITE_BIT) < 0) 288 return 0; 289 290 return 1; 291 } 292 293 static __inline__ int 294 __i2c_write(u8 *data, int length) 295 { 296 int i; 297 298 for (i = 0; i < length; i++) { 299 writeb(data[i], &i2c_dev[i2c_bus_num]->dr); 300 301 if (i2c_wait(I2C_WRITE_BIT) < 0) 302 break; 303 } 304 305 return i; 306 } 307 308 static __inline__ int 309 __i2c_read(u8 *data, int length) 310 { 311 int i; 312 313 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0), 314 &i2c_dev[i2c_bus_num]->cr); 315 316 /* dummy read */ 317 readb(&i2c_dev[i2c_bus_num]->dr); 318 319 for (i = 0; i < length; i++) { 320 if (i2c_wait(I2C_READ_BIT) < 0) 321 break; 322 323 /* Generate ack on last next to last byte */ 324 if (i == length - 2) 325 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK, 326 &i2c_dev[i2c_bus_num]->cr); 327 328 /* Generate stop on last byte */ 329 if (i == length - 1) 330 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr); 331 332 data[i] = readb(&i2c_dev[i2c_bus_num]->dr); 333 } 334 335 return i; 336 } 337 338 int 339 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) 340 { 341 int i = -1; /* signal error */ 342 u8 *a = (u8*)&addr; 343 344 if (i2c_wait4bus() >= 0 345 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 346 && __i2c_write(&a[4 - alen], alen) == alen) 347 i = 0; /* No error so far */ 348 349 if (length 350 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) 351 i = __i2c_read(data, length); 352 353 if (length && i2c_wait4bus()) /* Wait until STOP */ 354 debug("i2c_read: wait4bus timed out\n"); 355 356 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 357 358 if (i == length) 359 return 0; 360 361 return -1; 362 } 363 364 int 365 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) 366 { 367 int i = -1; /* signal error */ 368 u8 *a = (u8*)&addr; 369 370 if (i2c_wait4bus() >= 0 371 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0 372 && __i2c_write(&a[4 - alen], alen) == alen) { 373 i = __i2c_write(data, length); 374 } 375 376 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); 377 if (i2c_wait4bus()) /* Wait until STOP */ 378 debug("i2c_write: wait4bus timed out\n"); 379 380 if (i == length) 381 return 0; 382 383 return -1; 384 } 385 386 int 387 i2c_probe(uchar chip) 388 { 389 /* For unknow reason the controller will ACK when 390 * probing for a slave with the same address, so skip 391 * it. 392 */ 393 if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1)) 394 return -1; 395 396 return i2c_read(chip, 0, 0, NULL, 0); 397 } 398 399 int i2c_set_bus_num(unsigned int bus) 400 { 401 #if defined(CONFIG_I2C_MUX) 402 if (bus < CONFIG_SYS_MAX_I2C_BUS) { 403 i2c_bus_num = bus; 404 } else { 405 int ret; 406 407 ret = i2x_mux_select_mux(bus); 408 if (ret) 409 return ret; 410 i2c_bus_num = 0; 411 } 412 i2c_bus_num_mux = bus; 413 #else 414 #ifdef CONFIG_SYS_I2C2_OFFSET 415 if (bus > 1) { 416 #else 417 if (bus > 0) { 418 #endif 419 return -1; 420 } 421 422 i2c_bus_num = bus; 423 #endif 424 return 0; 425 } 426 427 int i2c_set_bus_speed(unsigned int speed) 428 { 429 unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; 430 431 writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ 432 i2c_bus_speed[i2c_bus_num] = 433 set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); 434 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ 435 436 return 0; 437 } 438 439 unsigned int i2c_get_bus_num(void) 440 { 441 #if defined(CONFIG_I2C_MUX) 442 return i2c_bus_num_mux; 443 #else 444 return i2c_bus_num; 445 #endif 446 } 447 448 unsigned int i2c_get_bus_speed(void) 449 { 450 return i2c_bus_speed[i2c_bus_num]; 451 } 452 453 #endif /* CONFIG_HARD_I2C */ 454