1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/arch/hardware.h> 11 #include "designware_i2c.h" 12 13 #ifdef CONFIG_I2C_MULTI_BUS 14 static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX]; 15 static unsigned int current_bus = 0; 16 #endif 17 18 static struct i2c_regs *i2c_regs_p = 19 (struct i2c_regs *)CONFIG_SYS_I2C_BASE; 20 21 /* 22 * set_speed - Set the i2c speed mode (standard, high, fast) 23 * @i2c_spd: required i2c speed mode 24 * 25 * Set the i2c speed mode (standard, high, fast) 26 */ 27 static void set_speed(int i2c_spd) 28 { 29 unsigned int cntl; 30 unsigned int hcnt, lcnt; 31 unsigned int enbl; 32 33 /* to set speed cltr must be disabled */ 34 enbl = readl(&i2c_regs_p->ic_enable); 35 enbl &= ~IC_ENABLE_0B; 36 writel(enbl, &i2c_regs_p->ic_enable); 37 38 cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK)); 39 40 switch (i2c_spd) { 41 case IC_SPEED_MODE_MAX: 42 cntl |= IC_CON_SPD_HS; 43 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; 44 writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt); 45 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; 46 writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt); 47 break; 48 49 case IC_SPEED_MODE_STANDARD: 50 cntl |= IC_CON_SPD_SS; 51 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; 52 writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt); 53 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; 54 writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt); 55 break; 56 57 case IC_SPEED_MODE_FAST: 58 default: 59 cntl |= IC_CON_SPD_FS; 60 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; 61 writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt); 62 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; 63 writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt); 64 break; 65 } 66 67 writel(cntl, &i2c_regs_p->ic_con); 68 69 /* Enable back i2c now speed set */ 70 enbl |= IC_ENABLE_0B; 71 writel(enbl, &i2c_regs_p->ic_enable); 72 } 73 74 /* 75 * i2c_set_bus_speed - Set the i2c speed 76 * @speed: required i2c speed 77 * 78 * Set the i2c speed. 79 */ 80 int i2c_set_bus_speed(int speed) 81 { 82 if (speed >= I2C_MAX_SPEED) 83 set_speed(IC_SPEED_MODE_MAX); 84 else if (speed >= I2C_FAST_SPEED) 85 set_speed(IC_SPEED_MODE_FAST); 86 else 87 set_speed(IC_SPEED_MODE_STANDARD); 88 89 return 0; 90 } 91 92 /* 93 * i2c_get_bus_speed - Gets the i2c speed 94 * 95 * Gets the i2c speed. 96 */ 97 int i2c_get_bus_speed(void) 98 { 99 u32 cntl; 100 101 cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK); 102 103 if (cntl == IC_CON_SPD_HS) 104 return I2C_MAX_SPEED; 105 else if (cntl == IC_CON_SPD_FS) 106 return I2C_FAST_SPEED; 107 else if (cntl == IC_CON_SPD_SS) 108 return I2C_STANDARD_SPEED; 109 110 return 0; 111 } 112 113 /* 114 * i2c_init - Init function 115 * @speed: required i2c speed 116 * @slaveadd: slave address for the device 117 * 118 * Initialization function. 119 */ 120 void i2c_init(int speed, int slaveadd) 121 { 122 unsigned int enbl; 123 124 /* Disable i2c */ 125 enbl = readl(&i2c_regs_p->ic_enable); 126 enbl &= ~IC_ENABLE_0B; 127 writel(enbl, &i2c_regs_p->ic_enable); 128 129 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con); 130 writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl); 131 writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl); 132 i2c_set_bus_speed(speed); 133 writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask); 134 writel(slaveadd, &i2c_regs_p->ic_sar); 135 136 /* Enable i2c */ 137 enbl = readl(&i2c_regs_p->ic_enable); 138 enbl |= IC_ENABLE_0B; 139 writel(enbl, &i2c_regs_p->ic_enable); 140 141 #ifdef CONFIG_I2C_MULTI_BUS 142 bus_initialized[current_bus] = 1; 143 #endif 144 } 145 146 /* 147 * i2c_setaddress - Sets the target slave address 148 * @i2c_addr: target i2c address 149 * 150 * Sets the target slave address. 151 */ 152 static void i2c_setaddress(unsigned int i2c_addr) 153 { 154 unsigned int enbl; 155 156 /* Disable i2c */ 157 enbl = readl(&i2c_regs_p->ic_enable); 158 enbl &= ~IC_ENABLE_0B; 159 writel(enbl, &i2c_regs_p->ic_enable); 160 161 writel(i2c_addr, &i2c_regs_p->ic_tar); 162 163 /* Enable i2c */ 164 enbl = readl(&i2c_regs_p->ic_enable); 165 enbl |= IC_ENABLE_0B; 166 writel(enbl, &i2c_regs_p->ic_enable); 167 } 168 169 /* 170 * i2c_flush_rxfifo - Flushes the i2c RX FIFO 171 * 172 * Flushes the i2c RX FIFO 173 */ 174 static void i2c_flush_rxfifo(void) 175 { 176 while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) 177 readl(&i2c_regs_p->ic_cmd_data); 178 } 179 180 /* 181 * i2c_wait_for_bb - Waits for bus busy 182 * 183 * Waits for bus busy 184 */ 185 static int i2c_wait_for_bb(void) 186 { 187 unsigned long start_time_bb = get_timer(0); 188 189 while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) || 190 !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) { 191 192 /* Evaluate timeout */ 193 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) 194 return 1; 195 } 196 197 return 0; 198 } 199 200 static int i2c_xfer_init(uchar chip, uint addr, int alen) 201 { 202 if (i2c_wait_for_bb()) 203 return 1; 204 205 i2c_setaddress(chip); 206 while (alen) { 207 alen--; 208 /* high byte address going out first */ 209 writel((addr >> (alen * 8)) & 0xff, 210 &i2c_regs_p->ic_cmd_data); 211 } 212 return 0; 213 } 214 215 static int i2c_xfer_finish(void) 216 { 217 ulong start_stop_det = get_timer(0); 218 219 while (1) { 220 if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) { 221 readl(&i2c_regs_p->ic_clr_stop_det); 222 break; 223 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { 224 break; 225 } 226 } 227 228 if (i2c_wait_for_bb()) { 229 printf("Timed out waiting for bus\n"); 230 return 1; 231 } 232 233 i2c_flush_rxfifo(); 234 235 return 0; 236 } 237 238 /* 239 * i2c_read - Read from i2c memory 240 * @chip: target i2c address 241 * @addr: address to read from 242 * @alen: 243 * @buffer: buffer for read data 244 * @len: no of bytes to be read 245 * 246 * Read from i2c memory. 247 */ 248 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 249 { 250 unsigned long start_time_rx; 251 252 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 253 /* 254 * EEPROM chips that implement "address overflow" are ones 255 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 256 * address and the extra bits end up in the "chip address" 257 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 258 * four 256 byte chips. 259 * 260 * Note that we consider the length of the address field to 261 * still be one byte because the extra address bits are 262 * hidden in the chip address. 263 */ 264 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 265 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 266 267 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, 268 addr); 269 #endif 270 271 if (i2c_xfer_init(chip, addr, alen)) 272 return 1; 273 274 start_time_rx = get_timer(0); 275 while (len) { 276 if (len == 1) 277 writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data); 278 else 279 writel(IC_CMD, &i2c_regs_p->ic_cmd_data); 280 281 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) { 282 *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data); 283 len--; 284 start_time_rx = get_timer(0); 285 286 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { 287 return 1; 288 } 289 } 290 291 return i2c_xfer_finish(); 292 } 293 294 /* 295 * i2c_write - Write to i2c memory 296 * @chip: target i2c address 297 * @addr: address to read from 298 * @alen: 299 * @buffer: buffer for read data 300 * @len: no of bytes to be read 301 * 302 * Write to i2c memory. 303 */ 304 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 305 { 306 int nb = len; 307 unsigned long start_time_tx; 308 309 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 310 /* 311 * EEPROM chips that implement "address overflow" are ones 312 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 313 * address and the extra bits end up in the "chip address" 314 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 315 * four 256 byte chips. 316 * 317 * Note that we consider the length of the address field to 318 * still be one byte because the extra address bits are 319 * hidden in the chip address. 320 */ 321 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 322 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 323 324 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip, 325 addr); 326 #endif 327 328 if (i2c_xfer_init(chip, addr, alen)) 329 return 1; 330 331 start_time_tx = get_timer(0); 332 while (len) { 333 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) { 334 if (--len == 0) 335 writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data); 336 else 337 writel(*buffer, &i2c_regs_p->ic_cmd_data); 338 buffer++; 339 start_time_tx = get_timer(0); 340 341 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { 342 printf("Timed out. i2c write Failed\n"); 343 return 1; 344 } 345 } 346 347 return i2c_xfer_finish(); 348 } 349 350 /* 351 * i2c_probe - Probe the i2c chip 352 */ 353 int i2c_probe(uchar chip) 354 { 355 u32 tmp; 356 int ret; 357 358 /* 359 * Try to read the first location of the chip. 360 */ 361 ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1); 362 if (ret) 363 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 364 365 return ret; 366 } 367 368 #ifdef CONFIG_I2C_MULTI_BUS 369 int i2c_set_bus_num(unsigned int bus) 370 { 371 switch (bus) { 372 case 0: 373 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE; 374 break; 375 #ifdef CONFIG_SYS_I2C_BASE1 376 case 1: 377 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1; 378 break; 379 #endif 380 #ifdef CONFIG_SYS_I2C_BASE2 381 case 2: 382 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2; 383 break; 384 #endif 385 #ifdef CONFIG_SYS_I2C_BASE3 386 case 3: 387 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3; 388 break; 389 #endif 390 #ifdef CONFIG_SYS_I2C_BASE4 391 case 4: 392 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4; 393 break; 394 #endif 395 #ifdef CONFIG_SYS_I2C_BASE5 396 case 5: 397 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5; 398 break; 399 #endif 400 #ifdef CONFIG_SYS_I2C_BASE6 401 case 6: 402 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6; 403 break; 404 #endif 405 #ifdef CONFIG_SYS_I2C_BASE7 406 case 7: 407 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7; 408 break; 409 #endif 410 #ifdef CONFIG_SYS_I2C_BASE8 411 case 8: 412 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8; 413 break; 414 #endif 415 #ifdef CONFIG_SYS_I2C_BASE9 416 case 9: 417 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9; 418 break; 419 #endif 420 default: 421 printf("Bad bus: %d\n", bus); 422 return -1; 423 } 424 425 current_bus = bus; 426 427 if (!bus_initialized[current_bus]) 428 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 429 430 return 0; 431 } 432 433 int i2c_get_bus_num(void) 434 { 435 return current_bus; 436 } 437 #endif 438