1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <i2c.h> 10 #include <asm/io.h> 11 #include "designware_i2c.h" 12 13 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) 14 { 15 u32 ena = enable ? IC_ENABLE_0B : 0; 16 int timeout = 100; 17 18 do { 19 writel(ena, &i2c_base->ic_enable); 20 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) 21 return; 22 23 /* 24 * Wait 10 times the signaling period of the highest I2C 25 * transfer supported by the driver (for 400KHz this is 26 * 25us) as described in the DesignWare I2C databook. 27 */ 28 udelay(25); 29 } while (timeout--); 30 31 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); 32 } 33 34 /* 35 * i2c_set_bus_speed - Set the i2c speed 36 * @speed: required i2c speed 37 * 38 * Set the i2c speed. 39 */ 40 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base, 41 unsigned int speed) 42 { 43 unsigned int cntl; 44 unsigned int hcnt, lcnt; 45 int i2c_spd; 46 47 if (speed >= I2C_MAX_SPEED) 48 i2c_spd = IC_SPEED_MODE_MAX; 49 else if (speed >= I2C_FAST_SPEED) 50 i2c_spd = IC_SPEED_MODE_FAST; 51 else 52 i2c_spd = IC_SPEED_MODE_STANDARD; 53 54 /* to set speed cltr must be disabled */ 55 dw_i2c_enable(i2c_base, false); 56 57 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); 58 59 switch (i2c_spd) { 60 case IC_SPEED_MODE_MAX: 61 cntl |= IC_CON_SPD_HS; 62 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; 63 writel(hcnt, &i2c_base->ic_hs_scl_hcnt); 64 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; 65 writel(lcnt, &i2c_base->ic_hs_scl_lcnt); 66 break; 67 68 case IC_SPEED_MODE_STANDARD: 69 cntl |= IC_CON_SPD_SS; 70 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; 71 writel(hcnt, &i2c_base->ic_ss_scl_hcnt); 72 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; 73 writel(lcnt, &i2c_base->ic_ss_scl_lcnt); 74 break; 75 76 case IC_SPEED_MODE_FAST: 77 default: 78 cntl |= IC_CON_SPD_FS; 79 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; 80 writel(hcnt, &i2c_base->ic_fs_scl_hcnt); 81 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; 82 writel(lcnt, &i2c_base->ic_fs_scl_lcnt); 83 break; 84 } 85 86 writel(cntl, &i2c_base->ic_con); 87 88 /* Enable back i2c now speed set */ 89 dw_i2c_enable(i2c_base, true); 90 91 return 0; 92 } 93 94 /* 95 * i2c_setaddress - Sets the target slave address 96 * @i2c_addr: target i2c address 97 * 98 * Sets the target slave address. 99 */ 100 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr) 101 { 102 /* Disable i2c */ 103 dw_i2c_enable(i2c_base, false); 104 105 writel(i2c_addr, &i2c_base->ic_tar); 106 107 /* Enable i2c */ 108 dw_i2c_enable(i2c_base, true); 109 } 110 111 /* 112 * i2c_flush_rxfifo - Flushes the i2c RX FIFO 113 * 114 * Flushes the i2c RX FIFO 115 */ 116 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base) 117 { 118 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) 119 readl(&i2c_base->ic_cmd_data); 120 } 121 122 /* 123 * i2c_wait_for_bb - Waits for bus busy 124 * 125 * Waits for bus busy 126 */ 127 static int i2c_wait_for_bb(struct i2c_regs *i2c_base) 128 { 129 unsigned long start_time_bb = get_timer(0); 130 131 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) || 132 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) { 133 134 /* Evaluate timeout */ 135 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) 136 return 1; 137 } 138 139 return 0; 140 } 141 142 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr, 143 int alen) 144 { 145 if (i2c_wait_for_bb(i2c_base)) 146 return 1; 147 148 i2c_setaddress(i2c_base, chip); 149 while (alen) { 150 alen--; 151 /* high byte address going out first */ 152 writel((addr >> (alen * 8)) & 0xff, 153 &i2c_base->ic_cmd_data); 154 } 155 return 0; 156 } 157 158 static int i2c_xfer_finish(struct i2c_regs *i2c_base) 159 { 160 ulong start_stop_det = get_timer(0); 161 162 while (1) { 163 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) { 164 readl(&i2c_base->ic_clr_stop_det); 165 break; 166 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { 167 break; 168 } 169 } 170 171 if (i2c_wait_for_bb(i2c_base)) { 172 printf("Timed out waiting for bus\n"); 173 return 1; 174 } 175 176 i2c_flush_rxfifo(i2c_base); 177 178 return 0; 179 } 180 181 /* 182 * i2c_read - Read from i2c memory 183 * @chip: target i2c address 184 * @addr: address to read from 185 * @alen: 186 * @buffer: buffer for read data 187 * @len: no of bytes to be read 188 * 189 * Read from i2c memory. 190 */ 191 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, 192 int alen, u8 *buffer, int len) 193 { 194 unsigned long start_time_rx; 195 196 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 197 /* 198 * EEPROM chips that implement "address overflow" are ones 199 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 200 * address and the extra bits end up in the "chip address" 201 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 202 * four 256 byte chips. 203 * 204 * Note that we consider the length of the address field to 205 * still be one byte because the extra address bits are 206 * hidden in the chip address. 207 */ 208 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 209 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 210 211 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 212 addr); 213 #endif 214 215 if (i2c_xfer_init(i2c_base, dev, addr, alen)) 216 return 1; 217 218 start_time_rx = get_timer(0); 219 while (len) { 220 if (len == 1) 221 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); 222 else 223 writel(IC_CMD, &i2c_base->ic_cmd_data); 224 225 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { 226 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); 227 len--; 228 start_time_rx = get_timer(0); 229 230 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { 231 return 1; 232 } 233 } 234 235 return i2c_xfer_finish(i2c_base); 236 } 237 238 /* 239 * i2c_write - Write to i2c memory 240 * @chip: target i2c address 241 * @addr: address to read from 242 * @alen: 243 * @buffer: buffer for read data 244 * @len: no of bytes to be read 245 * 246 * Write to i2c memory. 247 */ 248 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr, 249 int alen, u8 *buffer, int len) 250 { 251 int nb = len; 252 unsigned long start_time_tx; 253 254 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 255 /* 256 * EEPROM chips that implement "address overflow" are ones 257 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 258 * address and the extra bits end up in the "chip address" 259 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 260 * four 256 byte chips. 261 * 262 * Note that we consider the length of the address field to 263 * still be one byte because the extra address bits are 264 * hidden in the chip address. 265 */ 266 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 267 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 268 269 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 270 addr); 271 #endif 272 273 if (i2c_xfer_init(i2c_base, dev, addr, alen)) 274 return 1; 275 276 start_time_tx = get_timer(0); 277 while (len) { 278 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) { 279 if (--len == 0) { 280 writel(*buffer | IC_STOP, 281 &i2c_base->ic_cmd_data); 282 } else { 283 writel(*buffer, &i2c_base->ic_cmd_data); 284 } 285 buffer++; 286 start_time_tx = get_timer(0); 287 288 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { 289 printf("Timed out. i2c write Failed\n"); 290 return 1; 291 } 292 } 293 294 return i2c_xfer_finish(i2c_base); 295 } 296 297 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) 298 { 299 switch (adap->hwadapnr) { 300 #if CONFIG_SYS_I2C_BUS_MAX >= 4 301 case 3: 302 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; 303 #endif 304 #if CONFIG_SYS_I2C_BUS_MAX >= 3 305 case 2: 306 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; 307 #endif 308 #if CONFIG_SYS_I2C_BUS_MAX >= 2 309 case 1: 310 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; 311 #endif 312 case 0: 313 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; 314 default: 315 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr); 316 } 317 318 return NULL; 319 } 320 321 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, 322 unsigned int speed) 323 { 324 adap->speed = speed; 325 return __dw_i2c_set_bus_speed(i2c_get_base(adap), speed); 326 } 327 328 /* 329 * i2c_init - Init function 330 * @speed: required i2c speed 331 * @slaveaddr: slave address for the device 332 * 333 * Initialization function. 334 */ 335 static void dw_i2c_init(struct i2c_adapter *adap, int speed, 336 int slaveaddr) 337 { 338 struct i2c_regs *i2c_base = i2c_get_base(adap); 339 340 /* Disable i2c */ 341 dw_i2c_enable(i2c_base, false); 342 343 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); 344 writel(IC_RX_TL, &i2c_base->ic_rx_tl); 345 writel(IC_TX_TL, &i2c_base->ic_tx_tl); 346 dw_i2c_set_bus_speed(adap, speed); 347 writel(IC_STOP_DET, &i2c_base->ic_intr_mask); 348 writel(slaveaddr, &i2c_base->ic_sar); 349 350 /* Enable i2c */ 351 dw_i2c_enable(i2c_base, true); 352 } 353 354 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, 355 int alen, u8 *buffer, int len) 356 { 357 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len); 358 } 359 360 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, 361 int alen, u8 *buffer, int len) 362 { 363 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len); 364 } 365 366 /* 367 * i2c_probe - Probe the i2c chip 368 */ 369 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) 370 { 371 struct i2c_regs *i2c_base = i2c_get_base(adap); 372 u32 tmp; 373 int ret; 374 375 /* 376 * Try to read the first location of the chip. 377 */ 378 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1); 379 if (ret) 380 dw_i2c_init(adap, adap->speed, adap->slaveaddr); 381 382 return ret; 383 } 384 385 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 386 dw_i2c_write, dw_i2c_set_bus_speed, 387 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 388 389 #if CONFIG_SYS_I2C_BUS_MAX >= 2 390 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 391 dw_i2c_write, dw_i2c_set_bus_speed, 392 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) 393 #endif 394 395 #if CONFIG_SYS_I2C_BUS_MAX >= 3 396 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 397 dw_i2c_write, dw_i2c_set_bus_speed, 398 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) 399 #endif 400 401 #if CONFIG_SYS_I2C_BUS_MAX >= 4 402 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 403 dw_i2c_write, dw_i2c_set_bus_speed, 404 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) 405 #endif 406