1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <i2c.h> 10 #include <asm/io.h> 11 #include "designware_i2c.h" 12 13 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) 14 { 15 switch (adap->hwadapnr) { 16 #if CONFIG_SYS_I2C_BUS_MAX >= 4 17 case 3: 18 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; 19 #endif 20 #if CONFIG_SYS_I2C_BUS_MAX >= 3 21 case 2: 22 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; 23 #endif 24 #if CONFIG_SYS_I2C_BUS_MAX >= 2 25 case 1: 26 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; 27 #endif 28 case 0: 29 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; 30 default: 31 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr); 32 } 33 34 return NULL; 35 } 36 37 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) 38 { 39 u32 ena = enable ? IC_ENABLE_0B : 0; 40 int timeout = 100; 41 42 do { 43 writel(ena, &i2c_base->ic_enable); 44 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) 45 return; 46 47 /* 48 * Wait 10 times the signaling period of the highest I2C 49 * transfer supported by the driver (for 400KHz this is 50 * 25us) as described in the DesignWare I2C databook. 51 */ 52 udelay(25); 53 } while (timeout--); 54 55 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); 56 } 57 58 /* 59 * i2c_set_bus_speed - Set the i2c speed 60 * @speed: required i2c speed 61 * 62 * Set the i2c speed. 63 */ 64 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, 65 unsigned int speed) 66 { 67 struct i2c_regs *i2c_base = i2c_get_base(adap); 68 unsigned int cntl; 69 unsigned int hcnt, lcnt; 70 int i2c_spd; 71 72 if (speed >= I2C_MAX_SPEED) 73 i2c_spd = IC_SPEED_MODE_MAX; 74 else if (speed >= I2C_FAST_SPEED) 75 i2c_spd = IC_SPEED_MODE_FAST; 76 else 77 i2c_spd = IC_SPEED_MODE_STANDARD; 78 79 /* to set speed cltr must be disabled */ 80 dw_i2c_enable(i2c_base, false); 81 82 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); 83 84 switch (i2c_spd) { 85 case IC_SPEED_MODE_MAX: 86 cntl |= IC_CON_SPD_HS; 87 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO; 88 writel(hcnt, &i2c_base->ic_hs_scl_hcnt); 89 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO; 90 writel(lcnt, &i2c_base->ic_hs_scl_lcnt); 91 break; 92 93 case IC_SPEED_MODE_STANDARD: 94 cntl |= IC_CON_SPD_SS; 95 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO; 96 writel(hcnt, &i2c_base->ic_ss_scl_hcnt); 97 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO; 98 writel(lcnt, &i2c_base->ic_ss_scl_lcnt); 99 break; 100 101 case IC_SPEED_MODE_FAST: 102 default: 103 cntl |= IC_CON_SPD_FS; 104 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO; 105 writel(hcnt, &i2c_base->ic_fs_scl_hcnt); 106 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO; 107 writel(lcnt, &i2c_base->ic_fs_scl_lcnt); 108 break; 109 } 110 111 writel(cntl, &i2c_base->ic_con); 112 113 /* Enable back i2c now speed set */ 114 dw_i2c_enable(i2c_base, true); 115 116 adap->speed = speed; 117 118 return 0; 119 } 120 121 /* 122 * i2c_init - Init function 123 * @speed: required i2c speed 124 * @slaveaddr: slave address for the device 125 * 126 * Initialization function. 127 */ 128 static void dw_i2c_init(struct i2c_adapter *adap, int speed, 129 int slaveaddr) 130 { 131 struct i2c_regs *i2c_base = i2c_get_base(adap); 132 133 /* Disable i2c */ 134 dw_i2c_enable(i2c_base, false); 135 136 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con); 137 writel(IC_RX_TL, &i2c_base->ic_rx_tl); 138 writel(IC_TX_TL, &i2c_base->ic_tx_tl); 139 dw_i2c_set_bus_speed(adap, speed); 140 writel(IC_STOP_DET, &i2c_base->ic_intr_mask); 141 writel(slaveaddr, &i2c_base->ic_sar); 142 143 /* Enable i2c */ 144 dw_i2c_enable(i2c_base, true); 145 } 146 147 /* 148 * i2c_setaddress - Sets the target slave address 149 * @i2c_addr: target i2c address 150 * 151 * Sets the target slave address. 152 */ 153 static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr) 154 { 155 struct i2c_regs *i2c_base = i2c_get_base(adap); 156 157 /* Disable i2c */ 158 dw_i2c_enable(i2c_base, false); 159 160 writel(i2c_addr, &i2c_base->ic_tar); 161 162 /* Enable i2c */ 163 dw_i2c_enable(i2c_base, true); 164 } 165 166 /* 167 * i2c_flush_rxfifo - Flushes the i2c RX FIFO 168 * 169 * Flushes the i2c RX FIFO 170 */ 171 static void i2c_flush_rxfifo(struct i2c_adapter *adap) 172 { 173 struct i2c_regs *i2c_base = i2c_get_base(adap); 174 175 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) 176 readl(&i2c_base->ic_cmd_data); 177 } 178 179 /* 180 * i2c_wait_for_bb - Waits for bus busy 181 * 182 * Waits for bus busy 183 */ 184 static int i2c_wait_for_bb(struct i2c_adapter *adap) 185 { 186 struct i2c_regs *i2c_base = i2c_get_base(adap); 187 unsigned long start_time_bb = get_timer(0); 188 189 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) || 190 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) { 191 192 /* Evaluate timeout */ 193 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) 194 return 1; 195 } 196 197 return 0; 198 } 199 200 static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr, 201 int alen) 202 { 203 struct i2c_regs *i2c_base = i2c_get_base(adap); 204 205 if (i2c_wait_for_bb(adap)) 206 return 1; 207 208 i2c_setaddress(adap, chip); 209 while (alen) { 210 alen--; 211 /* high byte address going out first */ 212 writel((addr >> (alen * 8)) & 0xff, 213 &i2c_base->ic_cmd_data); 214 } 215 return 0; 216 } 217 218 static int i2c_xfer_finish(struct i2c_adapter *adap) 219 { 220 struct i2c_regs *i2c_base = i2c_get_base(adap); 221 ulong start_stop_det = get_timer(0); 222 223 while (1) { 224 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) { 225 readl(&i2c_base->ic_clr_stop_det); 226 break; 227 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { 228 break; 229 } 230 } 231 232 if (i2c_wait_for_bb(adap)) { 233 printf("Timed out waiting for bus\n"); 234 return 1; 235 } 236 237 i2c_flush_rxfifo(adap); 238 239 return 0; 240 } 241 242 /* 243 * i2c_read - Read from i2c memory 244 * @chip: target i2c address 245 * @addr: address to read from 246 * @alen: 247 * @buffer: buffer for read data 248 * @len: no of bytes to be read 249 * 250 * Read from i2c memory. 251 */ 252 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, 253 int alen, u8 *buffer, int len) 254 { 255 struct i2c_regs *i2c_base = i2c_get_base(adap); 256 unsigned long start_time_rx; 257 258 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 259 /* 260 * EEPROM chips that implement "address overflow" are ones 261 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 262 * address and the extra bits end up in the "chip address" 263 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 264 * four 256 byte chips. 265 * 266 * Note that we consider the length of the address field to 267 * still be one byte because the extra address bits are 268 * hidden in the chip address. 269 */ 270 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 271 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 272 273 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 274 addr); 275 #endif 276 277 if (i2c_xfer_init(adap, dev, addr, alen)) 278 return 1; 279 280 start_time_rx = get_timer(0); 281 while (len) { 282 if (len == 1) 283 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); 284 else 285 writel(IC_CMD, &i2c_base->ic_cmd_data); 286 287 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { 288 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); 289 len--; 290 start_time_rx = get_timer(0); 291 292 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { 293 return 1; 294 } 295 } 296 297 return i2c_xfer_finish(adap); 298 } 299 300 /* 301 * i2c_write - Write to i2c memory 302 * @chip: target i2c address 303 * @addr: address to read from 304 * @alen: 305 * @buffer: buffer for read data 306 * @len: no of bytes to be read 307 * 308 * Write to i2c memory. 309 */ 310 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, 311 int alen, u8 *buffer, int len) 312 { 313 struct i2c_regs *i2c_base = i2c_get_base(adap); 314 int nb = len; 315 unsigned long start_time_tx; 316 317 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 318 /* 319 * EEPROM chips that implement "address overflow" are ones 320 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 321 * address and the extra bits end up in the "chip address" 322 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 323 * four 256 byte chips. 324 * 325 * Note that we consider the length of the address field to 326 * still be one byte because the extra address bits are 327 * hidden in the chip address. 328 */ 329 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 330 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 331 332 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 333 addr); 334 #endif 335 336 if (i2c_xfer_init(adap, dev, addr, alen)) 337 return 1; 338 339 start_time_tx = get_timer(0); 340 while (len) { 341 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) { 342 if (--len == 0) { 343 writel(*buffer | IC_STOP, 344 &i2c_base->ic_cmd_data); 345 } else { 346 writel(*buffer, &i2c_base->ic_cmd_data); 347 } 348 buffer++; 349 start_time_tx = get_timer(0); 350 351 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { 352 printf("Timed out. i2c write Failed\n"); 353 return 1; 354 } 355 } 356 357 return i2c_xfer_finish(adap); 358 } 359 360 /* 361 * i2c_probe - Probe the i2c chip 362 */ 363 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) 364 { 365 u32 tmp; 366 int ret; 367 368 /* 369 * Try to read the first location of the chip. 370 */ 371 ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1); 372 if (ret) 373 dw_i2c_init(adap, adap->speed, adap->slaveaddr); 374 375 return ret; 376 } 377 378 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 379 dw_i2c_write, dw_i2c_set_bus_speed, 380 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 381 382 #if CONFIG_SYS_I2C_BUS_MAX >= 2 383 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 384 dw_i2c_write, dw_i2c_set_bus_speed, 385 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) 386 #endif 387 388 #if CONFIG_SYS_I2C_BUS_MAX >= 3 389 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 390 dw_i2c_write, dw_i2c_set_bus_speed, 391 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) 392 #endif 393 394 #if CONFIG_SYS_I2C_BUS_MAX >= 4 395 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 396 dw_i2c_write, dw_i2c_set_bus_speed, 397 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) 398 #endif 399