1 /* 2 * TI DaVinci (TMS320DM644x) I2C driver. 3 * 4 * (C) Copyright 2012-2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net> 7 * -------------------------------------------------------- 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 * 11 * NOTE: This driver should be converted to driver model before June 2017. 12 * Please see doc/driver-model/i2c-howto.txt for instructions. 13 */ 14 15 #include <common.h> 16 #include <i2c.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/i2c_defs.h> 19 #include <asm/io.h> 20 #include "davinci_i2c.h" 21 22 #define CHECK_NACK() \ 23 do {\ 24 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ 25 REG(&(i2c_base->i2c_con)) = 0;\ 26 return 1;\ 27 } \ 28 } while (0) 29 30 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap); 31 32 static int _wait_for_bus(struct i2c_regs *i2c_base) 33 { 34 int stat, timeout; 35 36 REG(&(i2c_base->i2c_stat)) = 0xffff; 37 38 for (timeout = 0; timeout < 10; timeout++) { 39 stat = REG(&(i2c_base->i2c_stat)); 40 if (!((stat) & I2C_STAT_BB)) { 41 REG(&(i2c_base->i2c_stat)) = 0xffff; 42 return 0; 43 } 44 45 REG(&(i2c_base->i2c_stat)) = stat; 46 udelay(50000); 47 } 48 49 REG(&(i2c_base->i2c_stat)) = 0xffff; 50 return 1; 51 } 52 53 static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask) 54 { 55 int stat, timeout; 56 57 for (timeout = 0; timeout < 10; timeout++) { 58 udelay(1000); 59 stat = REG(&(i2c_base->i2c_stat)); 60 if (stat & mask) 61 return stat; 62 } 63 64 REG(&(i2c_base->i2c_stat)) = 0xffff; 65 return stat | I2C_TIMEOUT; 66 } 67 68 static void _flush_rx(struct i2c_regs *i2c_base) 69 { 70 while (1) { 71 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) 72 break; 73 74 REG(&(i2c_base->i2c_drr)); 75 REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY; 76 udelay(1000); 77 } 78 } 79 80 static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base, 81 uint speed) 82 { 83 uint32_t div, psc; 84 85 psc = 2; 86 /* SCLL + SCLH */ 87 div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; 88 REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ 89 REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ 90 REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); 91 92 return 0; 93 } 94 95 static void _davinci_i2c_init(struct i2c_regs *i2c_base, 96 uint speed, int slaveadd) 97 { 98 if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) { 99 REG(&(i2c_base->i2c_con)) = 0; 100 udelay(50000); 101 } 102 103 _davinci_i2c_setspeed(i2c_base, speed); 104 105 REG(&(i2c_base->i2c_oa)) = slaveadd; 106 REG(&(i2c_base->i2c_cnt)) = 0; 107 108 /* Interrupts must be enabled or I2C module won't work */ 109 REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | 110 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; 111 112 /* Now enable I2C controller (get it out of reset) */ 113 REG(&(i2c_base->i2c_con)) = I2C_CON_EN; 114 115 udelay(1000); 116 } 117 118 static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip, 119 uint32_t addr, int alen, uint8_t *buf, int len) 120 { 121 uint32_t tmp; 122 int i; 123 124 if ((alen < 0) || (alen > 2)) { 125 printf("%s(): bogus address length %x\n", __func__, alen); 126 return 1; 127 } 128 129 if (_wait_for_bus(i2c_base)) 130 return 1; 131 132 if (alen != 0) { 133 /* Start address phase */ 134 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; 135 REG(&(i2c_base->i2c_cnt)) = alen; 136 REG(&(i2c_base->i2c_sa)) = chip; 137 REG(&(i2c_base->i2c_con)) = tmp; 138 139 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK); 140 141 CHECK_NACK(); 142 143 switch (alen) { 144 case 2: 145 /* Send address MSByte */ 146 if (tmp & I2C_STAT_XRDY) { 147 REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; 148 } else { 149 REG(&(i2c_base->i2c_con)) = 0; 150 return 1; 151 } 152 153 tmp = _poll_i2c_irq(i2c_base, 154 I2C_STAT_XRDY | I2C_STAT_NACK); 155 156 CHECK_NACK(); 157 /* No break, fall through */ 158 case 1: 159 /* Send address LSByte */ 160 if (tmp & I2C_STAT_XRDY) { 161 REG(&(i2c_base->i2c_dxr)) = addr & 0xff; 162 } else { 163 REG(&(i2c_base->i2c_con)) = 0; 164 return 1; 165 } 166 167 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | 168 I2C_STAT_NACK | I2C_STAT_ARDY); 169 170 CHECK_NACK(); 171 172 if (!(tmp & I2C_STAT_ARDY)) { 173 REG(&(i2c_base->i2c_con)) = 0; 174 return 1; 175 } 176 } 177 } 178 179 /* Address phase is over, now read 'len' bytes and stop */ 180 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; 181 REG(&(i2c_base->i2c_cnt)) = len & 0xffff; 182 REG(&(i2c_base->i2c_sa)) = chip; 183 REG(&(i2c_base->i2c_con)) = tmp; 184 185 for (i = 0; i < len; i++) { 186 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK | 187 I2C_STAT_ROVR); 188 189 CHECK_NACK(); 190 191 if (tmp & I2C_STAT_RRDY) { 192 buf[i] = REG(&(i2c_base->i2c_drr)); 193 } else { 194 REG(&(i2c_base->i2c_con)) = 0; 195 return 1; 196 } 197 } 198 199 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK); 200 201 CHECK_NACK(); 202 203 if (!(tmp & I2C_STAT_SCD)) { 204 REG(&(i2c_base->i2c_con)) = 0; 205 return 1; 206 } 207 208 _flush_rx(i2c_base); 209 REG(&(i2c_base->i2c_stat)) = 0xffff; 210 REG(&(i2c_base->i2c_cnt)) = 0; 211 REG(&(i2c_base->i2c_con)) = 0; 212 213 return 0; 214 } 215 216 static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip, 217 uint32_t addr, int alen, uint8_t *buf, int len) 218 { 219 uint32_t tmp; 220 int i; 221 222 if ((alen < 0) || (alen > 2)) { 223 printf("%s(): bogus address length %x\n", __func__, alen); 224 return 1; 225 } 226 if (len < 0) { 227 printf("%s(): bogus length %x\n", __func__, len); 228 return 1; 229 } 230 231 if (_wait_for_bus(i2c_base)) 232 return 1; 233 234 /* Start address phase */ 235 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 236 I2C_CON_TRX | I2C_CON_STP; 237 REG(&(i2c_base->i2c_cnt)) = (alen == 0) ? 238 len & 0xffff : (len & 0xffff) + alen; 239 REG(&(i2c_base->i2c_sa)) = chip; 240 REG(&(i2c_base->i2c_con)) = tmp; 241 242 switch (alen) { 243 case 2: 244 /* Send address MSByte */ 245 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK); 246 247 CHECK_NACK(); 248 249 if (tmp & I2C_STAT_XRDY) { 250 REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; 251 } else { 252 REG(&(i2c_base->i2c_con)) = 0; 253 return 1; 254 } 255 /* No break, fall through */ 256 case 1: 257 /* Send address LSByte */ 258 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK); 259 260 CHECK_NACK(); 261 262 if (tmp & I2C_STAT_XRDY) { 263 REG(&(i2c_base->i2c_dxr)) = addr & 0xff; 264 } else { 265 REG(&(i2c_base->i2c_con)) = 0; 266 return 1; 267 } 268 } 269 270 for (i = 0; i < len; i++) { 271 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK); 272 273 CHECK_NACK(); 274 275 if (tmp & I2C_STAT_XRDY) 276 REG(&(i2c_base->i2c_dxr)) = buf[i]; 277 else 278 return 1; 279 } 280 281 tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK); 282 283 CHECK_NACK(); 284 285 if (!(tmp & I2C_STAT_SCD)) { 286 REG(&(i2c_base->i2c_con)) = 0; 287 return 1; 288 } 289 290 _flush_rx(i2c_base); 291 REG(&(i2c_base->i2c_stat)) = 0xffff; 292 REG(&(i2c_base->i2c_cnt)) = 0; 293 REG(&(i2c_base->i2c_con)) = 0; 294 295 return 0; 296 } 297 298 static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip) 299 { 300 int rc = 1; 301 302 if (chip == REG(&(i2c_base->i2c_oa))) 303 return rc; 304 305 REG(&(i2c_base->i2c_con)) = 0; 306 if (_wait_for_bus(i2c_base)) 307 return 1; 308 309 /* try to read one byte from current (or only) address */ 310 REG(&(i2c_base->i2c_cnt)) = 1; 311 REG(&(i2c_base->i2c_sa)) = chip; 312 REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 313 I2C_CON_STP); 314 udelay(50000); 315 316 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) { 317 rc = 0; 318 _flush_rx(i2c_base); 319 REG(&(i2c_base->i2c_stat)) = 0xffff; 320 } else { 321 REG(&(i2c_base->i2c_stat)) = 0xffff; 322 REG(&(i2c_base->i2c_con)) |= I2C_CON_STP; 323 udelay(20000); 324 if (_wait_for_bus(i2c_base)) 325 return 1; 326 } 327 328 _flush_rx(i2c_base); 329 REG(&(i2c_base->i2c_stat)) = 0xffff; 330 REG(&(i2c_base->i2c_cnt)) = 0; 331 return rc; 332 } 333 334 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap) 335 { 336 switch (adap->hwadapnr) { 337 #if I2C_BUS_MAX >= 3 338 case 2: 339 return (struct i2c_regs *)I2C2_BASE; 340 #endif 341 #if I2C_BUS_MAX >= 2 342 case 1: 343 return (struct i2c_regs *)I2C1_BASE; 344 #endif 345 case 0: 346 return (struct i2c_regs *)I2C_BASE; 347 348 default: 349 printf("wrong hwadapnr: %d\n", adap->hwadapnr); 350 } 351 352 return NULL; 353 } 354 355 static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed) 356 { 357 struct i2c_regs *i2c_base = davinci_get_base(adap); 358 uint ret; 359 360 adap->speed = speed; 361 ret = _davinci_i2c_setspeed(i2c_base, speed); 362 363 return ret; 364 } 365 366 static void davinci_i2c_init(struct i2c_adapter *adap, int speed, 367 int slaveadd) 368 { 369 struct i2c_regs *i2c_base = davinci_get_base(adap); 370 371 adap->speed = speed; 372 _davinci_i2c_init(i2c_base, speed, slaveadd); 373 374 return; 375 } 376 377 static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip, 378 uint32_t addr, int alen, uint8_t *buf, int len) 379 { 380 struct i2c_regs *i2c_base = davinci_get_base(adap); 381 return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len); 382 } 383 384 static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip, 385 uint32_t addr, int alen, uint8_t *buf, int len) 386 { 387 struct i2c_regs *i2c_base = davinci_get_base(adap); 388 389 return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len); 390 } 391 392 static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip) 393 { 394 struct i2c_regs *i2c_base = davinci_get_base(adap); 395 396 return _davinci_i2c_probe_chip(i2c_base, chip); 397 } 398 399 U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip, 400 davinci_i2c_read, davinci_i2c_write, 401 davinci_i2c_setspeed, 402 CONFIG_SYS_DAVINCI_I2C_SPEED, 403 CONFIG_SYS_DAVINCI_I2C_SLAVE, 404 0) 405 406 #if I2C_BUS_MAX >= 2 407 U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip, 408 davinci_i2c_read, davinci_i2c_write, 409 davinci_i2c_setspeed, 410 CONFIG_SYS_DAVINCI_I2C_SPEED1, 411 CONFIG_SYS_DAVINCI_I2C_SLAVE1, 412 1) 413 #endif 414 415 #if I2C_BUS_MAX >= 3 416 U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip, 417 davinci_i2c_read, davinci_i2c_write, 418 davinci_i2c_setspeed, 419 CONFIG_SYS_DAVINCI_I2C_SPEED2, 420 CONFIG_SYS_DAVINCI_I2C_SLAVE2, 421 2) 422 #endif 423