1*8800e0faSSongjun Wu #ifndef _AT91_I2C_H 2*8800e0faSSongjun Wu #define _AT91_I2C_H 3*8800e0faSSongjun Wu 4*8800e0faSSongjun Wu #define TWI_CR_START BIT(0) /* Send a Start Condition */ 5*8800e0faSSongjun Wu #define TWI_CR_MSEN BIT(2) /* Master Transfer Enable */ 6*8800e0faSSongjun Wu #define TWI_CR_STOP BIT(1) /* Send a Stop Condition */ 7*8800e0faSSongjun Wu #define TWI_CR_SVDIS BIT(5) /* Slave Transfer Disable */ 8*8800e0faSSongjun Wu #define TWI_CR_SWRST BIT(7) /* Software Reset */ 9*8800e0faSSongjun Wu #define TWI_CR_ACMEN BIT(16) /* Alternative Command Mode Enable */ 10*8800e0faSSongjun Wu #define TWI_CR_ACMDIS BIT(17) /* Alternative Command Mode Disable */ 11*8800e0faSSongjun Wu #define TWI_CR_LOCKCLR BIT(26) /* Lock Clear */ 12*8800e0faSSongjun Wu 13*8800e0faSSongjun Wu #define TWI_MMR_MREAD BIT(12) /* Master Read Direction */ 14*8800e0faSSongjun Wu #define TWI_MMR_IADRSZ_1 BIT(8) /* Internal Device Address Size */ 15*8800e0faSSongjun Wu 16*8800e0faSSongjun Wu #define TWI_SR_TXCOMP BIT(0) /* Transmission Complete */ 17*8800e0faSSongjun Wu #define TWI_SR_RXRDY BIT(1) /* Receive Holding Register Ready */ 18*8800e0faSSongjun Wu #define TWI_SR_TXRDY BIT(2) /* Transmit Holding Register Ready */ 19*8800e0faSSongjun Wu #define TWI_SR_OVRE BIT(6) /* Overrun Error */ 20*8800e0faSSongjun Wu #define TWI_SR_UNRE BIT(7) /* Underrun Error */ 21*8800e0faSSongjun Wu #define TWI_SR_NACK BIT(8) /* Not Acknowledged */ 22*8800e0faSSongjun Wu #define TWI_SR_LOCK BIT(23) /* TWI Lock due to Frame Errors */ 23*8800e0faSSongjun Wu 24*8800e0faSSongjun Wu #define TWI_ACR_DATAL(len) ((len) & 0xff) 25*8800e0faSSongjun Wu #define TWI_ACR_DIR_READ BIT(8) 26*8800e0faSSongjun Wu 27*8800e0faSSongjun Wu #define TWI_CWGR_HOLD_MAX 0x1f 28*8800e0faSSongjun Wu #define TWI_CWGR_HOLD(x) (((x) & TWI_CWGR_HOLD_MAX) << 24) 29*8800e0faSSongjun Wu 30*8800e0faSSongjun Wu struct at91_i2c_regs { 31*8800e0faSSongjun Wu u32 cr; 32*8800e0faSSongjun Wu u32 mmr; 33*8800e0faSSongjun Wu u32 smr; 34*8800e0faSSongjun Wu u32 iadr; 35*8800e0faSSongjun Wu u32 cwgr; 36*8800e0faSSongjun Wu u32 rev_0[3]; 37*8800e0faSSongjun Wu u32 sr; 38*8800e0faSSongjun Wu u32 ier; 39*8800e0faSSongjun Wu u32 idr; 40*8800e0faSSongjun Wu u32 imr; 41*8800e0faSSongjun Wu u32 rhr; 42*8800e0faSSongjun Wu u32 thr; 43*8800e0faSSongjun Wu u32 smbtr; 44*8800e0faSSongjun Wu u32 rev_1; 45*8800e0faSSongjun Wu u32 acr; 46*8800e0faSSongjun Wu u32 filtr; 47*8800e0faSSongjun Wu u32 rev_2; 48*8800e0faSSongjun Wu u32 swmr; 49*8800e0faSSongjun Wu u32 fmr; 50*8800e0faSSongjun Wu u32 flr; 51*8800e0faSSongjun Wu u32 rev_3; 52*8800e0faSSongjun Wu u32 fsr; 53*8800e0faSSongjun Wu u32 fier; 54*8800e0faSSongjun Wu u32 fidr; 55*8800e0faSSongjun Wu u32 fimr; 56*8800e0faSSongjun Wu u32 rev_4[29]; 57*8800e0faSSongjun Wu u32 wpmr; 58*8800e0faSSongjun Wu u32 wpsr; 59*8800e0faSSongjun Wu u32 rev_5[6]; 60*8800e0faSSongjun Wu }; 61*8800e0faSSongjun Wu 62*8800e0faSSongjun Wu struct at91_i2c_pdata { 63*8800e0faSSongjun Wu unsigned clk_max_div; 64*8800e0faSSongjun Wu unsigned clk_offset; 65*8800e0faSSongjun Wu }; 66*8800e0faSSongjun Wu 67*8800e0faSSongjun Wu struct at91_i2c_bus { 68*8800e0faSSongjun Wu struct at91_i2c_regs *regs; 69*8800e0faSSongjun Wu u32 status; 70*8800e0faSSongjun Wu ulong bus_clk_rate; 71*8800e0faSSongjun Wu u32 clock_frequency; 72*8800e0faSSongjun Wu u32 speed; 73*8800e0faSSongjun Wu u32 cwgr_val; 74*8800e0faSSongjun Wu const struct at91_i2c_pdata *pdata; 75*8800e0faSSongjun Wu }; 76*8800e0faSSongjun Wu 77*8800e0faSSongjun Wu #endif 78