1 /* 2 * NVIDIA Tegra20 GPIO handling. 3 * (C) Copyright 2010-2012 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 /* 10 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver. 11 * Tom Warren (twarren@nvidia.com) 12 */ 13 14 #include <common.h> 15 #include <dm.h> 16 #include <malloc.h> 17 #include <errno.h> 18 #include <fdtdec.h> 19 #include <asm/io.h> 20 #include <asm/bitops.h> 21 #include <asm/arch/tegra.h> 22 #include <asm/gpio.h> 23 #include <dm/device-internal.h> 24 #include <dt-bindings/gpio/gpio.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 struct tegra_gpio_platdata { 29 struct gpio_ctlr_bank *bank; 30 const char *port_name; /* Name of port, e.g. "B" */ 31 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 32 }; 33 34 /* Information about each port at run-time */ 35 struct tegra_port_info { 36 struct gpio_ctlr_bank *bank; 37 int base_gpio; /* Port number for this port (0, 1,.., n-1) */ 38 }; 39 40 /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ 41 static int get_config(unsigned gpio) 42 { 43 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 44 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 45 u32 u; 46 int type; 47 48 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 49 type = (u >> GPIO_BIT(gpio)) & 1; 50 51 debug("get_config: port = %d, bit = %d is %s\n", 52 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 53 54 return type; 55 } 56 57 /* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */ 58 static void set_config(unsigned gpio, int type) 59 { 60 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 61 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 62 u32 u; 63 64 debug("set_config: port = %d, bit = %d, %s\n", 65 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); 66 67 u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); 68 if (type) /* GPIO */ 69 u |= 1 << GPIO_BIT(gpio); 70 else 71 u &= ~(1 << GPIO_BIT(gpio)); 72 writel(u, &bank->gpio_config[GPIO_PORT(gpio)]); 73 } 74 75 /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */ 76 static int get_direction(unsigned gpio) 77 { 78 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 79 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 80 u32 u; 81 int dir; 82 83 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 84 dir = (u >> GPIO_BIT(gpio)) & 1; 85 86 debug("get_direction: port = %d, bit = %d, %s\n", 87 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN"); 88 89 return dir; 90 } 91 92 /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */ 93 static void set_direction(unsigned gpio, int output) 94 { 95 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 96 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 97 u32 u; 98 99 debug("set_direction: port = %d, bit = %d, %s\n", 100 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN"); 101 102 u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]); 103 if (output) 104 u |= 1 << GPIO_BIT(gpio); 105 else 106 u &= ~(1 << GPIO_BIT(gpio)); 107 writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]); 108 } 109 110 /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */ 111 static void set_level(unsigned gpio, int high) 112 { 113 struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 114 struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; 115 u32 u; 116 117 debug("set_level: port = %d, bit %d == %d\n", 118 GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high); 119 120 u = readl(&bank->gpio_out[GPIO_PORT(gpio)]); 121 if (high) 122 u |= 1 << GPIO_BIT(gpio); 123 else 124 u &= ~(1 << GPIO_BIT(gpio)); 125 writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); 126 } 127 128 /* 129 * Generic_GPIO primitives. 130 */ 131 132 /* set GPIO pin 'gpio' as an input */ 133 static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) 134 { 135 struct tegra_port_info *state = dev_get_priv(dev); 136 137 /* Configure GPIO direction as input. */ 138 set_direction(state->base_gpio + offset, 0); 139 140 /* Enable the pin as a GPIO */ 141 set_config(state->base_gpio + offset, 1); 142 143 return 0; 144 } 145 146 /* set GPIO pin 'gpio' as an output, with polarity 'value' */ 147 static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, 148 int value) 149 { 150 struct tegra_port_info *state = dev_get_priv(dev); 151 int gpio = state->base_gpio + offset; 152 153 /* Configure GPIO output value. */ 154 set_level(gpio, value); 155 156 /* Configure GPIO direction as output. */ 157 set_direction(gpio, 1); 158 159 /* Enable the pin as a GPIO */ 160 set_config(state->base_gpio + offset, 1); 161 162 return 0; 163 } 164 165 /* read GPIO IN value of pin 'gpio' */ 166 static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) 167 { 168 struct tegra_port_info *state = dev_get_priv(dev); 169 int gpio = state->base_gpio + offset; 170 int val; 171 172 debug("%s: pin = %d (port %d:bit %d)\n", __func__, 173 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); 174 175 val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); 176 177 return (val >> GPIO_BIT(gpio)) & 1; 178 } 179 180 /* write GPIO OUT value to pin 'gpio' */ 181 static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value) 182 { 183 struct tegra_port_info *state = dev_get_priv(dev); 184 int gpio = state->base_gpio + offset; 185 186 debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", 187 gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); 188 189 /* Configure GPIO output value. */ 190 set_level(gpio, value); 191 192 return 0; 193 } 194 195 void gpio_config_table(const struct tegra_gpio_config *config, int len) 196 { 197 int i; 198 199 for (i = 0; i < len; i++) { 200 switch (config[i].init) { 201 case TEGRA_GPIO_INIT_IN: 202 set_direction(config[i].gpio, 0); 203 break; 204 case TEGRA_GPIO_INIT_OUT0: 205 set_level(config[i].gpio, 0); 206 set_direction(config[i].gpio, 1); 207 break; 208 case TEGRA_GPIO_INIT_OUT1: 209 set_level(config[i].gpio, 1); 210 set_direction(config[i].gpio, 1); 211 break; 212 } 213 set_config(config[i].gpio, 1); 214 } 215 } 216 217 static int tegra_gpio_get_function(struct udevice *dev, unsigned offset) 218 { 219 struct tegra_port_info *state = dev_get_priv(dev); 220 int gpio = state->base_gpio + offset; 221 222 if (!get_config(gpio)) 223 return GPIOF_FUNC; 224 else if (get_direction(gpio)) 225 return GPIOF_OUTPUT; 226 else 227 return GPIOF_INPUT; 228 } 229 230 static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, 231 struct fdtdec_phandle_args *args) 232 { 233 int gpio, port, ret; 234 235 gpio = args->args[0]; 236 port = gpio / TEGRA_GPIOS_PER_PORT; 237 ret = device_get_child(dev, port, &desc->dev); 238 if (ret) 239 return ret; 240 desc->offset = gpio % TEGRA_GPIOS_PER_PORT; 241 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; 242 243 return 0; 244 } 245 246 static const struct dm_gpio_ops gpio_tegra_ops = { 247 .direction_input = tegra_gpio_direction_input, 248 .direction_output = tegra_gpio_direction_output, 249 .get_value = tegra_gpio_get_value, 250 .set_value = tegra_gpio_set_value, 251 .get_function = tegra_gpio_get_function, 252 .xlate = tegra_gpio_xlate, 253 }; 254 255 /** 256 * Returns the name of a GPIO port 257 * 258 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ... 259 * 260 * @base_port: Base port number (0, 1..n-1) 261 * @return allocated string containing the name 262 */ 263 static char *gpio_port_name(int base_port) 264 { 265 char *name, *s; 266 267 name = malloc(3); 268 if (name) { 269 s = name; 270 *s++ = 'A' + (base_port % 26); 271 if (base_port >= 26) 272 *s++ = *name; 273 *s = '\0'; 274 } 275 276 return name; 277 } 278 279 static const struct udevice_id tegra_gpio_ids[] = { 280 { .compatible = "nvidia,tegra30-gpio" }, 281 { .compatible = "nvidia,tegra20-gpio" }, 282 { } 283 }; 284 285 static int gpio_tegra_probe(struct udevice *dev) 286 { 287 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 288 struct tegra_port_info *priv = dev->priv; 289 struct tegra_gpio_platdata *plat = dev->platdata; 290 291 /* Only child devices have ports */ 292 if (!plat) 293 return 0; 294 295 priv->bank = plat->bank; 296 priv->base_gpio = plat->base_gpio; 297 298 uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; 299 uc_priv->bank_name = plat->port_name; 300 301 return 0; 302 } 303 304 /** 305 * We have a top-level GPIO device with no actual GPIOs. It has a child 306 * device for each Tegra port. 307 */ 308 static int gpio_tegra_bind(struct udevice *parent) 309 { 310 struct tegra_gpio_platdata *plat = parent->platdata; 311 struct gpio_ctlr *ctlr; 312 int bank_count; 313 int bank; 314 int ret; 315 316 /* If this is a child device, there is nothing to do here */ 317 if (plat) 318 return 0; 319 320 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ 321 #ifdef CONFIG_SPL_BUILD 322 ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; 323 bank_count = TEGRA_GPIO_BANKS; 324 #else 325 { 326 int len; 327 328 /* 329 * This driver does not make use of interrupts, other than to figure 330 * out the number of GPIO banks 331 */ 332 if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len)) 333 return -EINVAL; 334 bank_count = len / 3 / sizeof(u32); 335 ctlr = (struct gpio_ctlr *)dev_get_addr(parent); 336 } 337 #endif 338 for (bank = 0; bank < bank_count; bank++) { 339 int port; 340 341 for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { 342 struct tegra_gpio_platdata *plat; 343 struct udevice *dev; 344 int base_port; 345 346 plat = calloc(1, sizeof(*plat)); 347 if (!plat) 348 return -ENOMEM; 349 plat->bank = &ctlr->gpio_bank[bank]; 350 base_port = bank * TEGRA_PORTS_PER_BANK + port; 351 plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; 352 plat->port_name = gpio_port_name(base_port); 353 354 ret = device_bind(parent, parent->driver, 355 plat->port_name, plat, -1, &dev); 356 if (ret) 357 return ret; 358 dev->of_offset = parent->of_offset; 359 } 360 } 361 362 return 0; 363 } 364 365 U_BOOT_DRIVER(gpio_tegra) = { 366 .name = "gpio_tegra", 367 .id = UCLASS_GPIO, 368 .of_match = tegra_gpio_ids, 369 .bind = gpio_tegra_bind, 370 .probe = gpio_tegra_probe, 371 .priv_auto_alloc_size = sizeof(struct tegra_port_info), 372 .ops = &gpio_tegra_ops, 373 .flags = DM_FLAG_PRE_RELOC, 374 }; 375