1*074a1fddSStephen Warren /* 2*074a1fddSStephen Warren * Copyright (c) 2016, NVIDIA CORPORATION. 3*074a1fddSStephen Warren * 4*074a1fddSStephen Warren * SPDX-License-Identifier: GPL-2.0 5*074a1fddSStephen Warren */ 6*074a1fddSStephen Warren 7*074a1fddSStephen Warren #ifndef _TEGRA186_GPIO_PRIV_H_ 8*074a1fddSStephen Warren #define _TEGRA186_GPIO_PRIV_H_ 9*074a1fddSStephen Warren 10*074a1fddSStephen Warren /* 11*074a1fddSStephen Warren * For each GPIO, there are a set of registers than affect it, all packed 12*074a1fddSStephen Warren * back-to-back. 13*074a1fddSStephen Warren */ 14*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 15*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) 16*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) 17*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SHIFT 2 18*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK 3 19*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE 0 20*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL 1 21*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE 2 22*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE 3 23*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL_HIGH_RISING BIT(4) 24*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE_ENABLE BIT(5) 25*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT_ENABLE BIT(6) 26*074a1fddSStephen Warren #define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMPING_ENABLE BIT(7) 27*074a1fddSStephen Warren 28*074a1fddSStephen Warren #define TEGRA186_GPIO_DEBOUNCE_THRESHOLD 0x04 29*074a1fddSStephen Warren 30*074a1fddSStephen Warren #define TEGRA186_GPIO_INPUT 0x08 31*074a1fddSStephen Warren 32*074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c 33*074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) 34*074a1fddSStephen Warren 35*074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 36*074a1fddSStephen Warren #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH 1 37*074a1fddSStephen Warren 38*074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 39*074a1fddSStephen Warren 40*074a1fddSStephen Warren /* 41*074a1fddSStephen Warren * 8 GPIOs are packed into a port. Their registers appear back-to-back in the 42*074a1fddSStephen Warren * port's address space. 43*074a1fddSStephen Warren */ 44*074a1fddSStephen Warren #define TEGRA186_GPIO_PER_GPIO_STRIDE 0x20 45*074a1fddSStephen Warren #define TEGRA186_GPIO_PER_GPIO_COUNT 8 46*074a1fddSStephen Warren 47*074a1fddSStephen Warren /* 48*074a1fddSStephen Warren * Per-port registers are packed immediately following all of a port's 49*074a1fddSStephen Warren * per-GPIO registers. 50*074a1fddSStephen Warren */ 51*074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_STATUS_G 0x100 52*074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_STATUS_G_STRIDE 4 53*074a1fddSStephen Warren #define TEGRA186_GPIO_INTERRUPT_STATUS_G_COUNT 8 54*074a1fddSStephen Warren 55*074a1fddSStephen Warren /* 56*074a1fddSStephen Warren * The registers for multiple ports are packed together back-to-back to form 57*074a1fddSStephen Warren * the overall controller. 58*074a1fddSStephen Warren */ 59*074a1fddSStephen Warren #define TEGRA186_GPIO_PER_PORT_STRIDE 0x200 60*074a1fddSStephen Warren 61*074a1fddSStephen Warren #endif 62