1 /* 2 * (C) Copyright 2011 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * 5 * (C) Copyright 2015 6 * Kamil Lulko, <rev13@wp.pl> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <asm/io.h> 13 #include <asm/errno.h> 14 #include <asm/arch/stm32.h> 15 #include <asm/arch/gpio.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) 20 #define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) 21 #define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) 22 #define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) 23 #define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) 24 #define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) 25 #define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) 26 #define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) 27 #define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) 28 29 static const unsigned long io_base[] = { 30 STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE, 31 STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE, 32 STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE 33 }; 34 35 struct stm32_gpio_regs { 36 u32 moder; /* GPIO port mode */ 37 u32 otyper; /* GPIO port output type */ 38 u32 ospeedr; /* GPIO port output speed */ 39 u32 pupdr; /* GPIO port pull-up/pull-down */ 40 u32 idr; /* GPIO port input data */ 41 u32 odr; /* GPIO port output data */ 42 u32 bsrr; /* GPIO port bit set/reset */ 43 u32 lckr; /* GPIO port configuration lock */ 44 u32 afr[2]; /* GPIO alternate function */ 45 }; 46 47 #define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15) 48 #define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \ 49 x->pupd > 2 || x->speed > 3) 50 51 int stm32_gpio_config(const struct stm32_gpio_dsc *dsc, 52 const struct stm32_gpio_ctl *ctl) 53 { 54 struct stm32_gpio_regs *gpio_regs; 55 u32 i; 56 int rv; 57 58 if (CHECK_DSC(dsc)) { 59 rv = -EINVAL; 60 goto out; 61 } 62 if (CHECK_CTL(ctl)) { 63 rv = -EINVAL; 64 goto out; 65 } 66 67 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; 68 69 setbits_le32(&STM32_RCC->ahb1enr, 1 << dsc->port); 70 71 i = (dsc->pin & 0x07) * 4; 72 clrbits_le32(&gpio_regs->afr[dsc->pin >> 3], (0xF << i)); 73 setbits_le32(&gpio_regs->afr[dsc->pin >> 3], ctl->af << i); 74 75 i = dsc->pin * 2; 76 77 clrbits_le32(&gpio_regs->moder, (0x3 << i)); 78 setbits_le32(&gpio_regs->moder, ctl->mode << i); 79 80 clrbits_le32(&gpio_regs->otyper, (0x3 << i)); 81 setbits_le32(&gpio_regs->otyper, ctl->otype << i); 82 83 clrbits_le32(&gpio_regs->ospeedr, (0x3 << i)); 84 setbits_le32(&gpio_regs->ospeedr, ctl->speed << i); 85 86 clrbits_le32(&gpio_regs->pupdr, (0x3 << i)); 87 setbits_le32(&gpio_regs->pupdr, ctl->pupd << i); 88 89 rv = 0; 90 out: 91 return rv; 92 } 93 94 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state) 95 { 96 struct stm32_gpio_regs *gpio_regs; 97 int rv; 98 99 if (CHECK_DSC(dsc)) { 100 rv = -EINVAL; 101 goto out; 102 } 103 104 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; 105 106 if (state) 107 writel(1 << dsc->pin, &gpio_regs->bsrr); 108 else 109 writel(1 << (dsc->pin + 16), &gpio_regs->bsrr); 110 111 rv = 0; 112 out: 113 return rv; 114 } 115 116 int stm32_gpin_get(const struct stm32_gpio_dsc *dsc) 117 { 118 struct stm32_gpio_regs *gpio_regs; 119 int rv; 120 121 if (CHECK_DSC(dsc)) { 122 rv = -EINVAL; 123 goto out; 124 } 125 126 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port]; 127 rv = readl(&gpio_regs->idr) & (1 << dsc->pin); 128 out: 129 return rv; 130 } 131 132 /* Common GPIO API */ 133 134 int gpio_request(unsigned gpio, const char *label) 135 { 136 return 0; 137 } 138 139 int gpio_free(unsigned gpio) 140 { 141 return 0; 142 } 143 144 int gpio_direction_input(unsigned gpio) 145 { 146 struct stm32_gpio_dsc dsc; 147 struct stm32_gpio_ctl ctl; 148 149 dsc.port = stm32_gpio_to_port(gpio); 150 dsc.pin = stm32_gpio_to_pin(gpio); 151 ctl.af = STM32_GPIO_AF0; 152 ctl.mode = STM32_GPIO_MODE_IN; 153 ctl.pupd = STM32_GPIO_PUPD_NO; 154 ctl.speed = STM32_GPIO_SPEED_50M; 155 156 return stm32_gpio_config(&dsc, &ctl); 157 } 158 159 int gpio_direction_output(unsigned gpio, int value) 160 { 161 struct stm32_gpio_dsc dsc; 162 struct stm32_gpio_ctl ctl; 163 int res; 164 165 dsc.port = stm32_gpio_to_port(gpio); 166 dsc.pin = stm32_gpio_to_pin(gpio); 167 ctl.af = STM32_GPIO_AF0; 168 ctl.mode = STM32_GPIO_MODE_OUT; 169 ctl.otype = STM32_GPIO_OTYPE_PP; 170 ctl.pupd = STM32_GPIO_PUPD_NO; 171 ctl.speed = STM32_GPIO_SPEED_50M; 172 173 res = stm32_gpio_config(&dsc, &ctl); 174 if (res < 0) 175 goto out; 176 res = stm32_gpout_set(&dsc, value); 177 out: 178 return res; 179 } 180 181 int gpio_get_value(unsigned gpio) 182 { 183 struct stm32_gpio_dsc dsc; 184 185 dsc.port = stm32_gpio_to_port(gpio); 186 dsc.pin = stm32_gpio_to_pin(gpio); 187 188 return stm32_gpin_get(&dsc); 189 } 190 191 int gpio_set_value(unsigned gpio, int value) 192 { 193 struct stm32_gpio_dsc dsc; 194 195 dsc.port = stm32_gpio_to_port(gpio); 196 dsc.pin = stm32_gpio_to_pin(gpio); 197 198 return stm32_gpout_set(&dsc, value); 199 } 200