1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * (C) Copyright 2008-2020 Rockchip Electronics 5 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 6 * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <syscon.h> 14 #include <linux/errno.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <dm/pinctrl.h> 19 #include <dt-bindings/clock/rk3288-cru.h> 20 21 enum { 22 ROCKCHIP_GPIOS_PER_BANK = 32, 23 }; 24 25 #define OFFSET_TO_BIT(bit) (1UL << (bit)) 26 27 #ifdef CONFIG_ROCKCHIP_GPIO_V2 28 #define REG_L(R) (R##_l) 29 #define REG_H(R) (R##_h) 30 #define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \ 31 ((readl(REG_H(REG)) & 0xFFFF) << 16)) 32 #define WRITE_REG(REG, VAL) \ 33 {\ 34 writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \ 35 writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\ 36 } 37 #define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK)) 38 #define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK)) 39 #define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \ 40 (READ_REG(REG) & ~(MASK)) | (VAL)) 41 42 #else 43 #define READ_REG(REG) readl(REG) 44 #define WRITE_REG(REG, VAL) writel(VAL, REG) 45 #define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK) 46 #define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK) 47 #define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL) 48 #endif 49 50 51 struct rockchip_gpio_priv { 52 struct rockchip_gpio_regs *regs; 53 struct udevice *pinctrl; 54 int bank; 55 char name[2]; 56 }; 57 58 static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset) 59 { 60 struct rockchip_gpio_priv *priv = dev_get_priv(dev); 61 struct rockchip_gpio_regs *regs = priv->regs; 62 63 CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset)); 64 65 return 0; 66 } 67 68 static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset, 69 int value) 70 { 71 struct rockchip_gpio_priv *priv = dev_get_priv(dev); 72 struct rockchip_gpio_regs *regs = priv->regs; 73 int mask = OFFSET_TO_BIT(offset); 74 75 CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0); 76 SETBITS_LE32(®s->swport_ddr, mask); 77 78 return 0; 79 } 80 81 static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset) 82 { 83 struct rockchip_gpio_priv *priv = dev_get_priv(dev); 84 struct rockchip_gpio_regs *regs = priv->regs; 85 86 return readl(®s->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0; 87 } 88 89 static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset, 90 int value) 91 { 92 struct rockchip_gpio_priv *priv = dev_get_priv(dev); 93 struct rockchip_gpio_regs *regs = priv->regs; 94 int mask = OFFSET_TO_BIT(offset); 95 96 CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0); 97 98 return 0; 99 } 100 101 static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) 102 { 103 #ifdef CONFIG_SPL_BUILD 104 return -ENODATA; 105 #else 106 struct rockchip_gpio_priv *priv = dev_get_priv(dev); 107 struct rockchip_gpio_regs *regs = priv->regs; 108 bool is_output; 109 int ret; 110 111 ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); 112 if (ret) 113 return ret; 114 115 /* If it's not 0, then it is not a GPIO */ 116 if (ret) 117 return GPIOF_FUNC; 118 119 is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset); 120 121 return is_output ? GPIOF_OUTPUT : GPIOF_INPUT; 122 #endif 123 } 124 125 static int rockchip_gpio_probe(struct udevice *dev) 126 { 127 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); 128 struct rockchip_gpio_priv *priv = dev_get_priv(dev); 129 char *end; 130 int pins_num; 131 int ret; 132 133 priv->regs = dev_read_addr_ptr(dev); 134 ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); 135 if (ret) 136 return ret; 137 138 uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; 139 end = strrchr(dev->name, '@'); 140 priv->bank = trailing_strtoln(dev->name, end); 141 priv->name[0] = 'A' + priv->bank; 142 uc_priv->bank_name = priv->name; 143 144 pins_num = pinctrl_get_pins_count(priv->pinctrl); 145 if (pins_num <= 0) { 146 printf("%s: fail to get pins from pinctrl\n", __func__); 147 } else if ((priv->bank + 1) * ROCKCHIP_GPIOS_PER_BANK >= pins_num) { 148 uc_priv->gpio_count = pins_num - priv->bank * ROCKCHIP_GPIOS_PER_BANK; 149 } 150 151 return 0; 152 } 153 154 static const struct dm_gpio_ops gpio_rockchip_ops = { 155 .direction_input = rockchip_gpio_direction_input, 156 .direction_output = rockchip_gpio_direction_output, 157 .get_value = rockchip_gpio_get_value, 158 .set_value = rockchip_gpio_set_value, 159 .get_function = rockchip_gpio_get_function, 160 }; 161 162 static const struct udevice_id rockchip_gpio_ids[] = { 163 { .compatible = "rockchip,gpio-bank" }, 164 { } 165 }; 166 167 U_BOOT_DRIVER(gpio_rockchip) = { 168 .name = "gpio_rockchip", 169 .id = UCLASS_GPIO, 170 .of_match = rockchip_gpio_ids, 171 .ops = &gpio_rockchip_ops, 172 .priv_auto_alloc_size = sizeof(struct rockchip_gpio_priv), 173 .probe = rockchip_gpio_probe, 174 }; 175