10c442298SAjay Bhargav /* 20c442298SAjay Bhargav * (C) Copyright 2011 30c442298SAjay Bhargav * eInfochips Ltd. <www.einfochips.com> 4*c7c47ca2SAjay Bhargav * Written-by: Ajay Bhargav <contact@8051projects.net> 50c442298SAjay Bhargav * 60c442298SAjay Bhargav * (C) Copyright 2010 70c442298SAjay Bhargav * Marvell Semiconductor <www.marvell.com> 80c442298SAjay Bhargav * 91a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 100c442298SAjay Bhargav */ 110c442298SAjay Bhargav 120c442298SAjay Bhargav #ifndef __MVGPIO_H__ 130c442298SAjay Bhargav #define __MVGPIO_H__ 140c442298SAjay Bhargav 150c442298SAjay Bhargav #include <common.h> 160c442298SAjay Bhargav 170c442298SAjay Bhargav /* 183d046f6aSZhou Zhu * GPIO Register map for Marvell SOCs 190c442298SAjay Bhargav */ 200c442298SAjay Bhargav struct gpio_reg { 210c442298SAjay Bhargav u32 gplr; /* Pin Level Register - 0x0000 */ 220c442298SAjay Bhargav u32 pad0[2]; 230c442298SAjay Bhargav u32 gpdr; /* Pin Direction Register - 0x000C */ 240c442298SAjay Bhargav u32 pad1[2]; 250c442298SAjay Bhargav u32 gpsr; /* Pin Output Set Register - 0x0018 */ 260c442298SAjay Bhargav u32 pad2[2]; 270c442298SAjay Bhargav u32 gpcr; /* Pin Output Clear Register - 0x0024 */ 280c442298SAjay Bhargav u32 pad3[2]; 290c442298SAjay Bhargav u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ 300c442298SAjay Bhargav u32 pad4[2]; 310c442298SAjay Bhargav u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ 320c442298SAjay Bhargav u32 pad5[2]; 330c442298SAjay Bhargav u32 gedr; /* Edge Detect Status Register - 0x0048 */ 340c442298SAjay Bhargav u32 pad6[2]; 350c442298SAjay Bhargav u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ 360c442298SAjay Bhargav u32 pad7[2]; 370c442298SAjay Bhargav u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ 380c442298SAjay Bhargav u32 pad8[2]; 390c442298SAjay Bhargav u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable 400c442298SAjay Bhargav Register - 0x006C */ 410c442298SAjay Bhargav u32 pad9[2]; 420c442298SAjay Bhargav u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable 430c442298SAjay Bhargav Register - 0x0078 */ 440c442298SAjay Bhargav u32 pad10[2]; 450c442298SAjay Bhargav u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable 460c442298SAjay Bhargav Register - 0x0084 */ 470c442298SAjay Bhargav u32 pad11[2]; 480c442298SAjay Bhargav u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable 490c442298SAjay Bhargav Register - 0x0090 */ 500c442298SAjay Bhargav u32 pad12[2]; 510c442298SAjay Bhargav u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ 520c442298SAjay Bhargav }; 530c442298SAjay Bhargav 540c442298SAjay Bhargav #endif /* __MVGPIO_H__ */ 55