1c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 2d5dae85fSMichal Simek * (C) Copyright 2012-2013, Xilinx, Michal Simek 3d5dae85fSMichal Simek * 4c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002 5c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 6c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Keith Outwater, keith_outwater@mvis.com 7c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 81a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 9c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 10c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 11c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 12c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Xilinx FPGA support 13c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 14c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 15c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <common.h> 166631db47SMichal Simek #include <fpga.h> 17c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <virtex2.h> 18c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <spartan2.h> 19c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <spartan3.h> 20d5dae85fSMichal Simek #include <zynqpl.h> 21c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 22c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if 0 23c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define FPGA_DEBUG 24c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 25c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 26c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Define FPGA_DEBUG to get debug printf's */ 27c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #ifdef FPGA_DEBUG 28c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define PRINTF(fmt,args...) printf (fmt ,##args) 29c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 30c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define PRINTF(fmt,args...) 31c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 32c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 33c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local Static Functions */ 34c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int xilinx_validate (Xilinx_desc * desc, char *fn); 35c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 36c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */ 37c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 3823f4bd75SMichal Simek int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) 3952c20644SMichal Simek { 4052c20644SMichal Simek unsigned int length; 4152c20644SMichal Simek unsigned int swapsize; 4252c20644SMichal Simek char buffer[80]; 4352c20644SMichal Simek unsigned char *dataptr; 4452c20644SMichal Simek unsigned int i; 456631db47SMichal Simek const fpga_desc *desc; 466631db47SMichal Simek Xilinx_desc *xdesc; 4752c20644SMichal Simek 4852c20644SMichal Simek dataptr = (unsigned char *)fpgadata; 496631db47SMichal Simek /* Find out fpga_description */ 506631db47SMichal Simek desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); 516631db47SMichal Simek /* Assign xilinx device description */ 526631db47SMichal Simek xdesc = desc->devdesc; 5352c20644SMichal Simek 5452c20644SMichal Simek /* skip the first bytes of the bitsteam, their meaning is unknown */ 5552c20644SMichal Simek length = (*dataptr << 8) + *(dataptr + 1); 5652c20644SMichal Simek dataptr += 2; 5752c20644SMichal Simek dataptr += length; 5852c20644SMichal Simek 5952c20644SMichal Simek /* get design name (identifier, length, string) */ 6052c20644SMichal Simek length = (*dataptr << 8) + *(dataptr + 1); 6152c20644SMichal Simek dataptr += 2; 6252c20644SMichal Simek if (*dataptr++ != 0x61) { 6352c20644SMichal Simek debug("%s: Design name id not recognized in bitstream\n", 6452c20644SMichal Simek __func__); 6552c20644SMichal Simek return FPGA_FAIL; 6652c20644SMichal Simek } 6752c20644SMichal Simek 6852c20644SMichal Simek length = (*dataptr << 8) + *(dataptr + 1); 6952c20644SMichal Simek dataptr += 2; 7052c20644SMichal Simek for (i = 0; i < length; i++) 7152c20644SMichal Simek buffer[i] = *dataptr++; 7252c20644SMichal Simek 7352c20644SMichal Simek printf(" design filename = \"%s\"\n", buffer); 7452c20644SMichal Simek 7552c20644SMichal Simek /* get part number (identifier, length, string) */ 7652c20644SMichal Simek if (*dataptr++ != 0x62) { 7752c20644SMichal Simek printf("%s: Part number id not recognized in bitstream\n", 7852c20644SMichal Simek __func__); 7952c20644SMichal Simek return FPGA_FAIL; 8052c20644SMichal Simek } 8152c20644SMichal Simek 8252c20644SMichal Simek length = (*dataptr << 8) + *(dataptr + 1); 8352c20644SMichal Simek dataptr += 2; 8452c20644SMichal Simek for (i = 0; i < length; i++) 8552c20644SMichal Simek buffer[i] = *dataptr++; 866631db47SMichal Simek 876631db47SMichal Simek if (xdesc->name) { 886631db47SMichal Simek i = strncmp(buffer, xdesc->name, strlen(xdesc->name)); 896631db47SMichal Simek if (i) { 906631db47SMichal Simek printf("%s: Wrong bitstream ID for this device\n", 916631db47SMichal Simek __func__); 926631db47SMichal Simek printf("%s: Bitstream ID %s, current device ID %d/%s\n", 936631db47SMichal Simek __func__, buffer, devnum, xdesc->name); 946631db47SMichal Simek return FPGA_FAIL; 956631db47SMichal Simek } 966631db47SMichal Simek } else { 976631db47SMichal Simek printf("%s: Please fill correct device ID to Xilinx_desc\n", 986631db47SMichal Simek __func__); 996631db47SMichal Simek } 10052c20644SMichal Simek printf(" part number = \"%s\"\n", buffer); 10152c20644SMichal Simek 10252c20644SMichal Simek /* get date (identifier, length, string) */ 10352c20644SMichal Simek if (*dataptr++ != 0x63) { 10452c20644SMichal Simek printf("%s: Date identifier not recognized in bitstream\n", 10552c20644SMichal Simek __func__); 10652c20644SMichal Simek return FPGA_FAIL; 10752c20644SMichal Simek } 10852c20644SMichal Simek 10952c20644SMichal Simek length = (*dataptr << 8) + *(dataptr+1); 11052c20644SMichal Simek dataptr += 2; 11152c20644SMichal Simek for (i = 0; i < length; i++) 11252c20644SMichal Simek buffer[i] = *dataptr++; 11352c20644SMichal Simek printf(" date = \"%s\"\n", buffer); 11452c20644SMichal Simek 11552c20644SMichal Simek /* get time (identifier, length, string) */ 11652c20644SMichal Simek if (*dataptr++ != 0x64) { 11752c20644SMichal Simek printf("%s: Time identifier not recognized in bitstream\n", 11852c20644SMichal Simek __func__); 11952c20644SMichal Simek return FPGA_FAIL; 12052c20644SMichal Simek } 12152c20644SMichal Simek 12252c20644SMichal Simek length = (*dataptr << 8) + *(dataptr+1); 12352c20644SMichal Simek dataptr += 2; 12452c20644SMichal Simek for (i = 0; i < length; i++) 12552c20644SMichal Simek buffer[i] = *dataptr++; 12652c20644SMichal Simek printf(" time = \"%s\"\n", buffer); 12752c20644SMichal Simek 12852c20644SMichal Simek /* get fpga data length (identifier, length) */ 12952c20644SMichal Simek if (*dataptr++ != 0x65) { 13052c20644SMichal Simek printf("%s: Data length id not recognized in bitstream\n", 13152c20644SMichal Simek __func__); 13252c20644SMichal Simek return FPGA_FAIL; 13352c20644SMichal Simek } 13452c20644SMichal Simek swapsize = ((unsigned int) *dataptr << 24) + 13552c20644SMichal Simek ((unsigned int) *(dataptr + 1) << 16) + 13652c20644SMichal Simek ((unsigned int) *(dataptr + 2) << 8) + 13752c20644SMichal Simek ((unsigned int) *(dataptr + 3)); 13852c20644SMichal Simek dataptr += 4; 13952c20644SMichal Simek printf(" bytes in bitstream = %d\n", swapsize); 14052c20644SMichal Simek 14123f4bd75SMichal Simek return fpga_load(devnum, dataptr, swapsize); 14252c20644SMichal Simek } 14352c20644SMichal Simek 144e6a857daSWolfgang Denk int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) 145c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 146c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume a failure */ 147c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 148c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 149c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid device descriptor\n", __FUNCTION__); 150c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else 151c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 152b625b9aeSMichal Simek case xilinx_spartan2: 153c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_SPARTAN2) 154c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Spartan-II Loader...\n", 155c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 156b625b9aeSMichal Simek ret_val = spartan2_load(desc, buf, bsize); 157c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 158c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Spartan-II devices.\n", 159c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 160c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 161c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 1622a6e3869SMichal Simek case xilinx_spartan3: 163c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_SPARTAN3) 164c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Spartan-III Loader...\n", 165c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 1662a6e3869SMichal Simek ret_val = spartan3_load(desc, buf, bsize); 167c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 168c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Spartan-III devices.\n", 169c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 170c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 171c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 172*d9071ce0SMichal Simek case xilinx_virtex2: 173c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_VIRTEX2) 174c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Virtex-II Loader...\n", 175c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 176*d9071ce0SMichal Simek ret_val = virtex2_load(desc, buf, bsize); 177c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 178c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Virtex-II devices.\n", 179c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 180c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 181c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 182d5dae85fSMichal Simek case xilinx_zynq: 183d5dae85fSMichal Simek #if defined(CONFIG_FPGA_ZYNQPL) 184d5dae85fSMichal Simek PRINTF("%s: Launching the Zynq PL Loader...\n", 185d5dae85fSMichal Simek __func__); 186d5dae85fSMichal Simek ret_val = zynq_load(desc, buf, bsize); 187d5dae85fSMichal Simek #else 188d5dae85fSMichal Simek printf("%s: No support for Zynq devices.\n", 189d5dae85fSMichal Simek __func__); 190d5dae85fSMichal Simek #endif 191d5dae85fSMichal Simek break; 192c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 193c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 194c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Unsupported family type, %d\n", 195c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__, desc->family); 196c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 197c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 198c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 199c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 200c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 201e6a857daSWolfgang Denk int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) 202c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 203c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume a failure */ 204c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 205c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!xilinx_validate (desc, (char *)__FUNCTION__)) { 206c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid device descriptor\n", __FUNCTION__); 207c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else 208c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 209b625b9aeSMichal Simek case xilinx_spartan2: 210c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_SPARTAN2) 211c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Spartan-II Reader...\n", 212c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 213b625b9aeSMichal Simek ret_val = spartan2_dump(desc, buf, bsize); 214c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 215c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Spartan-II devices.\n", 216c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 217c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 218c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 2192a6e3869SMichal Simek case xilinx_spartan3: 220c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_SPARTAN3) 221c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Spartan-III Reader...\n", 222c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 2232a6e3869SMichal Simek ret_val = spartan3_dump(desc, buf, bsize); 224c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 225c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Spartan-III devices.\n", 226c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 227c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 228c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 229*d9071ce0SMichal Simek case xilinx_virtex2: 230c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined( CONFIG_FPGA_VIRTEX2) 231c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Virtex-II Reader...\n", 232c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 233*d9071ce0SMichal Simek ret_val = virtex2_dump(desc, buf, bsize); 234c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 235c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Virtex-II devices.\n", 236c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 237c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 238c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 239d5dae85fSMichal Simek case xilinx_zynq: 240d5dae85fSMichal Simek #if defined(CONFIG_FPGA_ZYNQPL) 241d5dae85fSMichal Simek PRINTF("%s: Launching the Zynq PL Reader...\n", 242d5dae85fSMichal Simek __func__); 243d5dae85fSMichal Simek ret_val = zynq_dump(desc, buf, bsize); 244d5dae85fSMichal Simek #else 245d5dae85fSMichal Simek printf("%s: No support for Zynq devices.\n", 246d5dae85fSMichal Simek __func__); 247d5dae85fSMichal Simek #endif 248d5dae85fSMichal Simek break; 249c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 250c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 251c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Unsupported family type, %d\n", 252c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__, desc->family); 253c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 254c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 255c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 256c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 257c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 258c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int xilinx_info (Xilinx_desc * desc) 259c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 260c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; 261c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 262c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (xilinx_validate (desc, (char *)__FUNCTION__)) { 263c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Family: \t"); 264c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 265b625b9aeSMichal Simek case xilinx_spartan2: 266c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Spartan-II\n"); 267c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 2682a6e3869SMichal Simek case xilinx_spartan3: 269c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Spartan-III\n"); 270c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 271*d9071ce0SMichal Simek case xilinx_virtex2: 272c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Virtex-II\n"); 273c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 274d5dae85fSMichal Simek case xilinx_zynq: 275d5dae85fSMichal Simek printf("Zynq PL\n"); 276d5dae85fSMichal Simek break; 277c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Add new family types here */ 278c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 279c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Unknown family type, %d\n", desc->family); 280c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 281c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 282c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Interface type:\t"); 283c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->iface) { 284c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case slave_serial: 285c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Slave Serial\n"); 286c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 287c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case master_serial: /* Not used */ 288c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Master Serial\n"); 289c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 290c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case slave_parallel: 291c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Slave Parallel\n"); 292c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 293c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case jtag_mode: /* Not used */ 294c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("JTAG Mode\n"); 295c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 296c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case slave_selectmap: 297c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Slave SelectMap Mode\n"); 298c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 299c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case master_selectmap: 300c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Master SelectMap Mode\n"); 301c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 302d5dae85fSMichal Simek case devcfg: 303d5dae85fSMichal Simek printf("Device configuration interface (Zynq)\n"); 304d5dae85fSMichal Simek break; 305c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Add new interface types here */ 306c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 307c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Unsupported interface type, %d\n", desc->iface); 308c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 309c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 310c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Device Size: \t%d bytes\n" 311c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD "Cookie: \t0x%x (%d)\n", 312c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc->size, desc->cookie, desc->cookie); 3136631db47SMichal Simek if (desc->name) 3146631db47SMichal Simek printf("Device name: \t%s\n", desc->name); 315c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 316c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc->iface_fns) { 317c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Device Function Table @ 0x%p\n", desc->iface_fns); 318c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 319b625b9aeSMichal Simek case xilinx_spartan2: 320c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_SPARTAN2) 321b625b9aeSMichal Simek spartan2_info(desc); 322c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 323c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* just in case */ 324c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Spartan-II devices.\n", 325c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 326c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 327c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 3282a6e3869SMichal Simek case xilinx_spartan3: 329c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_SPARTAN3) 3302a6e3869SMichal Simek spartan3_info(desc); 331c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 332c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* just in case */ 333c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Spartan-III devices.\n", 334c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 335c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 336c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 337*d9071ce0SMichal Simek case xilinx_virtex2: 338c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_VIRTEX2) 339*d9071ce0SMichal Simek virtex2_info(desc); 340c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 341c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* just in case */ 342c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for Virtex-II devices.\n", 343c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 344c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 345c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 346d5dae85fSMichal Simek case xilinx_zynq: 347d5dae85fSMichal Simek #if defined(CONFIG_FPGA_ZYNQPL) 348d5dae85fSMichal Simek zynq_info(desc); 349d5dae85fSMichal Simek #else 350d5dae85fSMichal Simek /* just in case */ 351d5dae85fSMichal Simek printf("%s: No support for Zynq devices.\n", 352d5dae85fSMichal Simek __func__); 353d5dae85fSMichal Simek #endif 354c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Add new family types here */ 355c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 356c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* we don't need a message here - we give one up above */ 357c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ; 358c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 359c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else 360c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("No Device Function Table.\n"); 361c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 362c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = FPGA_SUCCESS; 363c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 364c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid device descriptor\n", __FUNCTION__); 365c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 366c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 367c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 368c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 369c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 370c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */ 371c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 372c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int xilinx_validate (Xilinx_desc * desc, char *fn) 373c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 374472d5460SYork Sun int ret_val = false; 375c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 376c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 377c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if ((desc->family > min_xilinx_type) && 378c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD (desc->family < max_xilinx_type)) { 379c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if ((desc->iface > min_xilinx_iface_type) && 380c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD (desc->iface < max_xilinx_iface_type)) { 381c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc->size) { 382472d5460SYork Sun ret_val = true; 383c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else 384c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: NULL part size\n", fn); 385c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else 386c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid Interface type, %d\n", 387c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fn, desc->iface); 388c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else 389c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid family type, %d\n", fn, desc->family); 390c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else 391c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: NULL descriptor!\n", fn); 392c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 393c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 394c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 395