1ff9c4c53SStefan Roese /*
2ff9c4c53SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3ff9c4c53SStefan Roese *
4ff9c4c53SStefan Roese * SPDX-License-Identifier: GPL-2.0+
5ff9c4c53SStefan Roese */
6ff9c4c53SStefan Roese
7ff9c4c53SStefan Roese #include <common.h>
8ff9c4c53SStefan Roese #include <altera.h>
9ff9c4c53SStefan Roese #include <spi.h>
10ff9c4c53SStefan Roese #include <asm/io.h>
11*1221ce45SMasahiro Yamada #include <linux/errno.h>
12ff9c4c53SStefan Roese
13ff9c4c53SStefan Roese /* Write the RBF data to FPGA via SPI */
program_write(int spi_bus,int spi_dev,const void * rbf_data,unsigned long rbf_size)14ff9c4c53SStefan Roese static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
15ff9c4c53SStefan Roese unsigned long rbf_size)
16ff9c4c53SStefan Roese {
17ff9c4c53SStefan Roese struct spi_slave *slave;
18ff9c4c53SStefan Roese int ret;
19ff9c4c53SStefan Roese
20ff9c4c53SStefan Roese debug("%s (%d): data=%p size=%ld\n",
21ff9c4c53SStefan Roese __func__, __LINE__, rbf_data, rbf_size);
22ff9c4c53SStefan Roese
23ff9c4c53SStefan Roese /* FIXME: How to get the max. SPI clock and SPI mode? */
24ff9c4c53SStefan Roese slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
25ff9c4c53SStefan Roese if (!slave)
26ff9c4c53SStefan Roese return -1;
27ff9c4c53SStefan Roese
28ff9c4c53SStefan Roese if (spi_claim_bus(slave))
29ff9c4c53SStefan Roese return -1;
30ff9c4c53SStefan Roese
31ff9c4c53SStefan Roese ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
32ff9c4c53SStefan Roese SPI_XFER_BEGIN | SPI_XFER_END);
33ff9c4c53SStefan Roese
34ff9c4c53SStefan Roese spi_release_bus(slave);
35ff9c4c53SStefan Roese
36ff9c4c53SStefan Roese return ret;
37ff9c4c53SStefan Roese }
38ff9c4c53SStefan Roese
39ff9c4c53SStefan Roese /*
40ff9c4c53SStefan Roese * This is the interface used by FPGA driver.
41ff9c4c53SStefan Roese * Return 0 for sucess, non-zero for error.
42ff9c4c53SStefan Roese */
stratixv_load(Altera_desc * desc,const void * rbf_data,size_t rbf_size)43ff9c4c53SStefan Roese int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
44ff9c4c53SStefan Roese {
45ff9c4c53SStefan Roese altera_board_specific_func *pfns = desc->iface_fns;
46ff9c4c53SStefan Roese int cookie = desc->cookie;
47ff9c4c53SStefan Roese int spi_bus;
48ff9c4c53SStefan Roese int spi_dev;
49ff9c4c53SStefan Roese int ret = 0;
50ff9c4c53SStefan Roese
51ff9c4c53SStefan Roese if ((u32)rbf_data & 0x3) {
52ff9c4c53SStefan Roese puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
53ff9c4c53SStefan Roese return -EINVAL;
54ff9c4c53SStefan Roese }
55ff9c4c53SStefan Roese
56ff9c4c53SStefan Roese /* Run the pre configuration function if there is one */
57ff9c4c53SStefan Roese if (pfns->pre)
58ff9c4c53SStefan Roese (pfns->pre)(cookie);
59ff9c4c53SStefan Roese
60ff9c4c53SStefan Roese /* Establish the initial state */
61ff9c4c53SStefan Roese if (pfns->config) {
62ff9c4c53SStefan Roese /* De-assert nCONFIG */
63ff9c4c53SStefan Roese (pfns->config)(false, true, cookie);
64ff9c4c53SStefan Roese
65ff9c4c53SStefan Roese /* nConfig minimum low pulse width is 2us */
66ff9c4c53SStefan Roese udelay(200);
67ff9c4c53SStefan Roese
68ff9c4c53SStefan Roese /* Assert nCONFIG */
69ff9c4c53SStefan Roese (pfns->config)(true, true, cookie);
70ff9c4c53SStefan Roese
71ff9c4c53SStefan Roese /* nCONFIG high to first rising clock on DCLK min 1506 us */
72ff9c4c53SStefan Roese udelay(1600);
73ff9c4c53SStefan Roese }
74ff9c4c53SStefan Roese
75ff9c4c53SStefan Roese /* Write the RBF data to FPGA */
76ff9c4c53SStefan Roese if (pfns->write) {
77ff9c4c53SStefan Roese /*
78ff9c4c53SStefan Roese * Use board specific data function to write bitstream
79ff9c4c53SStefan Roese * into the FPGA
80ff9c4c53SStefan Roese */
81ff9c4c53SStefan Roese ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
82ff9c4c53SStefan Roese } else {
83ff9c4c53SStefan Roese /*
84ff9c4c53SStefan Roese * Use common SPI functions to write bitstream into the
85ff9c4c53SStefan Roese * FPGA
86ff9c4c53SStefan Roese */
87ff9c4c53SStefan Roese spi_bus = COOKIE2SPI_BUS(cookie);
88ff9c4c53SStefan Roese spi_dev = COOKIE2SPI_DEV(cookie);
89ff9c4c53SStefan Roese ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
90ff9c4c53SStefan Roese }
91ff9c4c53SStefan Roese if (ret)
92ff9c4c53SStefan Roese return ret;
93ff9c4c53SStefan Roese
94ff9c4c53SStefan Roese /* Check done pin */
95ff9c4c53SStefan Roese if (pfns->done) {
96ff9c4c53SStefan Roese ret = (pfns->done)(cookie);
97ff9c4c53SStefan Roese
98ff9c4c53SStefan Roese if (ret)
99ff9c4c53SStefan Roese printf("Error: DONE not set (ret=%d)!\n", ret);
100ff9c4c53SStefan Roese }
101ff9c4c53SStefan Roese
102ff9c4c53SStefan Roese return ret;
103ff9c4c53SStefan Roese }
104