1c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 2c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002 3c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 5c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * See file CREDITS for list of people who contributed to this 6c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * project. 7c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 8c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 9c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 10c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 11c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 12c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 13c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 14c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 15c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 17c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 18c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 19c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 20c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 22c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 23c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 24c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 25f6555d90SMichal Simek /* Generic FPGA support */ 26c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <common.h> /* core U-Boot definitions */ 27c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <xilinx.h> /* xilinx specific definitions */ 28c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <altera.h> /* altera specific definitions */ 293b8ac464SStefano Babic #include <lattice.h> 30c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 31c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local definitions */ 32c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_MAX_FPGA_DEVICES 33c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_MAX_FPGA_DEVICES 5 34c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 35c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 36c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local static data */ 37c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int next_desc = FPGA_INVALID_DEVICE; 38c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; 39c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 40f6555d90SMichal Simek /* 41f6555d90SMichal Simek * fpga_no_sup 42c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 'no support' message function 43c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 44c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static void fpga_no_sup(char *fn, char *msg) 45c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 46f6555d90SMichal Simek if (fn && msg) 47c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: No support for %s.\n", fn, msg); 48f6555d90SMichal Simek else if (msg) 49c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("No support for %s.\n", msg); 50f6555d90SMichal Simek else 51c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("No FPGA suport!\n"); 52c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 53c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 54c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 55c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* fpga_get_desc 56c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * map a device number to a descriptor 57c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 58f6555d90SMichal Simek static const fpga_desc *const fpga_get_desc(int devnum) 59c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 60c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fpga_desc *desc = (fpga_desc *)NULL; 61c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 62c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if ((devnum >= 0) && (devnum < next_desc)) { 63c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc = &desc_table[devnum]; 64f6555d90SMichal Simek debug("%s: found fpga descriptor #%d @ 0x%p\n", 65f6555d90SMichal Simek __func__, devnum, desc); 66c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 67c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 68c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return desc; 69c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 70c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 71f6555d90SMichal Simek /* 72f6555d90SMichal Simek * fpga_validate 73c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic parameter checking code 74c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 75f6555d90SMichal Simek static const fpga_desc *const fpga_validate(int devnum, const void *buf, 76c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD size_t bsize, char *fn) 77c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 78f6555d90SMichal Simek const fpga_desc *desc = fpga_get_desc(devnum); 79c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 80f6555d90SMichal Simek if (!desc) 81c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid device number %d\n", fn, devnum); 82c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 83c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!buf) { 84c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Null buffer.\n", fn); 85c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return (fpga_desc * const)NULL; 86c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 87c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return desc; 88c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 89c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 90f6555d90SMichal Simek /* 91f6555d90SMichal Simek * fpga_dev_info 92c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic multiplexing code 93c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 94c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int fpga_dev_info(int devnum) 95c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 96c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */ 97c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD const fpga_desc * const desc = fpga_get_desc(devnum); 98c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 99c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 100f6555d90SMichal Simek debug("%s: Device Descriptor @ 0x%p\n", 101f6555d90SMichal Simek __func__, desc->devdesc); 102c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 103c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) { 104c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx: 105c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX) 106c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("Xilinx Device\nDescriptor @ 0x%p\n", desc); 107c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = xilinx_info(desc->devdesc); 108c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 109f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices"); 110c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 111c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 112c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera: 113c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA) 114c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("Altera Device\nDescriptor @ 0x%p\n", desc); 115c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_info(desc->devdesc); 116c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 117f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices"); 118c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 119c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 1203b8ac464SStefano Babic case fpga_lattice: 121439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE) 1223b8ac464SStefano Babic printf("Lattice Device\nDescriptor @ 0x%p\n", desc); 1233b8ac464SStefano Babic ret_val = lattice_info(desc->devdesc); 124439f6f7eSWolfgang Denk #else 125f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices"); 126439f6f7eSWolfgang Denk #endif 1273b8ac464SStefano Babic break; 128c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 129c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n", 130f6555d90SMichal Simek __func__, desc->devtype); 131c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 132c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 133f6555d90SMichal Simek printf("%s: Invalid device number %d\n", __func__, devnum); 134c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 135c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 136c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 137c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 138c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 139f6555d90SMichal Simek /* 140f6555d90SMichal Simek * fgpa_init is usually called from misc_init_r() and MUST be called 141c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * before any of the other fpga functions are used. 142c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 1436385b281SPeter Tyser void fpga_init(void) 144c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 145c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD next_desc = 0; 146c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD memset(desc_table, 0, sizeof(desc_table)); 147c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 148*ee976c1bSMichal Simek debug("%s\n", __func__); 149c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 150c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 151f6555d90SMichal Simek /* 152f6555d90SMichal Simek * fpga_count 153c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Basic interface function to get the current number of devices available. 154c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 155c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_count(void) 156c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 157c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return next_desc; 158c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 159c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 160f6555d90SMichal Simek /* 161f6555d90SMichal Simek * fpga_add 1626385b281SPeter Tyser * Add the device descriptor to the device table. 163c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 164c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_add(fpga_type devtype, void *desc) 165c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 166c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int devnum = FPGA_INVALID_DEVICE; 167c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 168c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc < 0) { 169f6555d90SMichal Simek printf("%s: FPGA support not initialized!\n", __func__); 170c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { 171c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 172c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc < CONFIG_MAX_FPGA_DEVICES) { 173c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD devnum = next_desc; 174c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc_table[next_desc].devtype = devtype; 175c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc_table[next_desc++].devdesc = desc; 176c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 177f6555d90SMichal Simek printf("%s: Exceeded Max FPGA device count\n", 178f6555d90SMichal Simek __func__); 179c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 180c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 181f6555d90SMichal Simek printf("%s: NULL device descriptor\n", __func__); 182c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 183c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 184f6555d90SMichal Simek printf("%s: Unsupported FPGA type %d\n", __func__, devtype); 185c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 186c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 187c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return devnum; 188c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 189c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 190c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 191c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Generic multiplexing code 192c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 193e6a857daSWolfgang Denk int fpga_load(int devnum, const void *buf, size_t bsize) 194c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 195c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */ 196f6555d90SMichal Simek const fpga_desc *desc = fpga_validate(devnum, buf, bsize, 197f6555d90SMichal Simek (char *)__func__); 198c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 199c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 200c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) { 201c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx: 202c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX) 203c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = xilinx_load(desc->devdesc, buf, bsize); 204c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 205f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices"); 206c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 207c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 208c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera: 209c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA) 210c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_load(desc->devdesc, buf, bsize); 211c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 212f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices"); 213c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 214c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 2153b8ac464SStefano Babic case fpga_lattice: 216439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE) 2173b8ac464SStefano Babic ret_val = lattice_load(desc->devdesc, buf, bsize); 218439f6f7eSWolfgang Denk #else 219f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices"); 220439f6f7eSWolfgang Denk #endif 2213b8ac464SStefano Babic break; 222c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 223c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n", 224f6555d90SMichal Simek __func__, desc->devtype); 225c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 226c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 227c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 228c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 229c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 230c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 231f6555d90SMichal Simek /* 232f6555d90SMichal Simek * fpga_dump 233c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic multiplexing code 234c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 235e6a857daSWolfgang Denk int fpga_dump(int devnum, const void *buf, size_t bsize) 236c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 237c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */ 238f6555d90SMichal Simek const fpga_desc *desc = fpga_validate(devnum, buf, bsize, 239f6555d90SMichal Simek (char *)__func__); 240c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 241c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 242c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) { 243c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx: 244c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX) 245c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = xilinx_dump(desc->devdesc, buf, bsize); 246c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 247f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices"); 248c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 249c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 250c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera: 251c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA) 252c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_dump(desc->devdesc, buf, bsize); 253c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 254f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices"); 255c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 256c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 2573b8ac464SStefano Babic case fpga_lattice: 258439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE) 2593b8ac464SStefano Babic ret_val = lattice_dump(desc->devdesc, buf, bsize); 260439f6f7eSWolfgang Denk #else 261f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices"); 262439f6f7eSWolfgang Denk #endif 2633b8ac464SStefano Babic break; 264c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 265c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n", 266f6555d90SMichal Simek __func__, desc->devtype); 267c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 268c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 269c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 270c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 271c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 272c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 273f6555d90SMichal Simek /* 274f6555d90SMichal Simek * fpga_info 275c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * front end to fpga_dev_info. If devnum is invalid, report on all 276c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * available devices. 277c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 278c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_info(int devnum) 279c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 280c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (devnum == FPGA_INVALID_DEVICE) { 281c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc > 0) { 282c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int dev; 283c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 284f6555d90SMichal Simek for (dev = 0; dev < next_desc; dev++) 285c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fpga_dev_info(dev); 286f6555d90SMichal Simek 287c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return FPGA_SUCCESS; 288c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 289f6555d90SMichal Simek printf("%s: No FPGA devices available.\n", __func__); 290c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return FPGA_FAIL; 291c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 292c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 293c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 294f6555d90SMichal Simek return fpga_dev_info(devnum); 295f6555d90SMichal Simek } 296