1c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 2c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002 3c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 7c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 8f6555d90SMichal Simek /* Generic FPGA support */ 9c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <common.h> /* core U-Boot definitions */ 10c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <xilinx.h> /* xilinx specific definitions */ 11c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <altera.h> /* altera specific definitions */ 123b8ac464SStefano Babic #include <lattice.h> 13c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 14c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local definitions */ 15c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_MAX_FPGA_DEVICES 16c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_MAX_FPGA_DEVICES 5 17c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 18c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 19c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local static data */ 20c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int next_desc = FPGA_INVALID_DEVICE; 21c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; 22c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 23f6555d90SMichal Simek /* 24f6555d90SMichal Simek * fpga_no_sup 25c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 'no support' message function 26c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 27c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static void fpga_no_sup(char *fn, char *msg) 28c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 29f6555d90SMichal Simek if (fn && msg) 30c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: No support for %s.\n", fn, msg); 31f6555d90SMichal Simek else if (msg) 32c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("No support for %s.\n", msg); 33f6555d90SMichal Simek else 34c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("No FPGA suport!\n"); 35c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 36c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 37c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 38c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* fpga_get_desc 39c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * map a device number to a descriptor 40c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 41ebd322deSMichal Simek const fpga_desc *const fpga_get_desc(int devnum) 42c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 43c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fpga_desc *desc = (fpga_desc *)NULL; 44c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 45c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if ((devnum >= 0) && (devnum < next_desc)) { 46c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc = &desc_table[devnum]; 47f6555d90SMichal Simek debug("%s: found fpga descriptor #%d @ 0x%p\n", 48f6555d90SMichal Simek __func__, devnum, desc); 49c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 50c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 51c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return desc; 52c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 53c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 54f6555d90SMichal Simek /* 55f6555d90SMichal Simek * fpga_validate 56c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic parameter checking code 57c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 586631db47SMichal Simek const fpga_desc *const fpga_validate(int devnum, const void *buf, 59c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD size_t bsize, char *fn) 60c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 61f6555d90SMichal Simek const fpga_desc *desc = fpga_get_desc(devnum); 62c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 63f6555d90SMichal Simek if (!desc) 64c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid device number %d\n", fn, devnum); 65c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 66c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!buf) { 67c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Null buffer.\n", fn); 68c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return (fpga_desc * const)NULL; 69c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 70c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return desc; 71c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 72c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 73f6555d90SMichal Simek /* 74f6555d90SMichal Simek * fpga_dev_info 75c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic multiplexing code 76c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 77c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int fpga_dev_info(int devnum) 78c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 79c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */ 80c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD const fpga_desc * const desc = fpga_get_desc(devnum); 81c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 82c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 83f6555d90SMichal Simek debug("%s: Device Descriptor @ 0x%p\n", 84f6555d90SMichal Simek __func__, desc->devdesc); 85c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 86c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) { 87c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx: 88c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX) 89c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("Xilinx Device\nDescriptor @ 0x%p\n", desc); 90c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = xilinx_info(desc->devdesc); 91c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 92f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices"); 93c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 94c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 95c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera: 96c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA) 97c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("Altera Device\nDescriptor @ 0x%p\n", desc); 98c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_info(desc->devdesc); 99c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 100f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices"); 101c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 102c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 1033b8ac464SStefano Babic case fpga_lattice: 104439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE) 1053b8ac464SStefano Babic printf("Lattice Device\nDescriptor @ 0x%p\n", desc); 1063b8ac464SStefano Babic ret_val = lattice_info(desc->devdesc); 107439f6f7eSWolfgang Denk #else 108f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices"); 109439f6f7eSWolfgang Denk #endif 1103b8ac464SStefano Babic break; 111c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 112c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n", 113f6555d90SMichal Simek __func__, desc->devtype); 114c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 115c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 116f6555d90SMichal Simek printf("%s: Invalid device number %d\n", __func__, devnum); 117c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 118c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 119c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 120c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 121c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 122f6555d90SMichal Simek /* 123*905bca6cSMichal Simek * fpga_init is usually called from misc_init_r() and MUST be called 124c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * before any of the other fpga functions are used. 125c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 1266385b281SPeter Tyser void fpga_init(void) 127c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 128c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD next_desc = 0; 129c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD memset(desc_table, 0, sizeof(desc_table)); 130c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 131ee976c1bSMichal Simek debug("%s\n", __func__); 132c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 133c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 134f6555d90SMichal Simek /* 135f6555d90SMichal Simek * fpga_count 136c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Basic interface function to get the current number of devices available. 137c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 138c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_count(void) 139c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 140c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return next_desc; 141c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 142c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 143f6555d90SMichal Simek /* 144f6555d90SMichal Simek * fpga_add 1456385b281SPeter Tyser * Add the device descriptor to the device table. 146c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 147c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_add(fpga_type devtype, void *desc) 148c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 149c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int devnum = FPGA_INVALID_DEVICE; 150c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 151c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc < 0) { 152f6555d90SMichal Simek printf("%s: FPGA support not initialized!\n", __func__); 153c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { 154c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 155c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc < CONFIG_MAX_FPGA_DEVICES) { 156c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD devnum = next_desc; 157c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc_table[next_desc].devtype = devtype; 158c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc_table[next_desc++].devdesc = desc; 159c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 160f6555d90SMichal Simek printf("%s: Exceeded Max FPGA device count\n", 161f6555d90SMichal Simek __func__); 162c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 163c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 164f6555d90SMichal Simek printf("%s: NULL device descriptor\n", __func__); 165c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 166c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 167f6555d90SMichal Simek printf("%s: Unsupported FPGA type %d\n", __func__, devtype); 168c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 169c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 170c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return devnum; 171c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 172c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 173c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 17452c20644SMichal Simek * Convert bitstream data and load into the fpga 17552c20644SMichal Simek */ 1767a78bd26SMichal Simek int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, 1777a78bd26SMichal Simek bitstream_type bstype) 17852c20644SMichal Simek { 17952c20644SMichal Simek printf("Bitstream support not implemented for this FPGA device\n"); 18052c20644SMichal Simek return FPGA_FAIL; 18152c20644SMichal Simek } 18252c20644SMichal Simek 1831a897668SSiva Durga Prasad Paladugu #if defined(CONFIG_CMD_FPGA_LOADFS) 1841a897668SSiva Durga Prasad Paladugu int fpga_fsload(int devnum, const void *buf, size_t size, 1851a897668SSiva Durga Prasad Paladugu fpga_fs_info *fpga_fsinfo) 1861a897668SSiva Durga Prasad Paladugu { 1871a897668SSiva Durga Prasad Paladugu int ret_val = FPGA_FAIL; /* assume failure */ 1881a897668SSiva Durga Prasad Paladugu const fpga_desc *desc = fpga_validate(devnum, buf, size, 1891a897668SSiva Durga Prasad Paladugu (char *)__func__); 1901a897668SSiva Durga Prasad Paladugu 1911a897668SSiva Durga Prasad Paladugu if (desc) { 1921a897668SSiva Durga Prasad Paladugu switch (desc->devtype) { 1931a897668SSiva Durga Prasad Paladugu case fpga_xilinx: 1941a897668SSiva Durga Prasad Paladugu #if defined(CONFIG_FPGA_XILINX) 1951a897668SSiva Durga Prasad Paladugu ret_val = xilinx_loadfs(desc->devdesc, buf, size, 1961a897668SSiva Durga Prasad Paladugu fpga_fsinfo); 1971a897668SSiva Durga Prasad Paladugu #else 1981a897668SSiva Durga Prasad Paladugu fpga_no_sup((char *)__func__, "Xilinx devices"); 1991a897668SSiva Durga Prasad Paladugu #endif 2001a897668SSiva Durga Prasad Paladugu break; 2011a897668SSiva Durga Prasad Paladugu default: 2021a897668SSiva Durga Prasad Paladugu printf("%s: Invalid or unsupported device type %d\n", 2031a897668SSiva Durga Prasad Paladugu __func__, desc->devtype); 2041a897668SSiva Durga Prasad Paladugu } 2051a897668SSiva Durga Prasad Paladugu } 2061a897668SSiva Durga Prasad Paladugu 2071a897668SSiva Durga Prasad Paladugu return ret_val; 2081a897668SSiva Durga Prasad Paladugu } 2091a897668SSiva Durga Prasad Paladugu #endif 2101a897668SSiva Durga Prasad Paladugu 21152c20644SMichal Simek /* 212c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Generic multiplexing code 213c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 2147a78bd26SMichal Simek int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype) 215c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 216c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */ 217f6555d90SMichal Simek const fpga_desc *desc = fpga_validate(devnum, buf, bsize, 218f6555d90SMichal Simek (char *)__func__); 219c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 220c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 221c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) { 222c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx: 223c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX) 2247a78bd26SMichal Simek ret_val = xilinx_load(desc->devdesc, buf, bsize, 2257a78bd26SMichal Simek bstype); 226c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 227f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices"); 228c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 229c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 230c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera: 231c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA) 232c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_load(desc->devdesc, buf, bsize); 233c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 234f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices"); 235c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 236c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 2373b8ac464SStefano Babic case fpga_lattice: 238439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE) 2393b8ac464SStefano Babic ret_val = lattice_load(desc->devdesc, buf, bsize); 240439f6f7eSWolfgang Denk #else 241f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices"); 242439f6f7eSWolfgang Denk #endif 2433b8ac464SStefano Babic break; 244c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 245c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n", 246f6555d90SMichal Simek __func__, desc->devtype); 247c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 248c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 249c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 250c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 251c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 252c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 253f6555d90SMichal Simek /* 254f6555d90SMichal Simek * fpga_dump 255c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * generic multiplexing code 256c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 257e6a857daSWolfgang Denk int fpga_dump(int devnum, const void *buf, size_t bsize) 258c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 259c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume failure */ 260f6555d90SMichal Simek const fpga_desc *desc = fpga_validate(devnum, buf, bsize, 261f6555d90SMichal Simek (char *)__func__); 262c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 263c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 264c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->devtype) { 265c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_xilinx: 266c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_XILINX) 267c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = xilinx_dump(desc->devdesc, buf, bsize); 268c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 269f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Xilinx devices"); 270c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 271c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 272c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fpga_altera: 273c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ALTERA) 274c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = altera_dump(desc->devdesc, buf, bsize); 275c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 276f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Altera devices"); 277c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 278c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 2793b8ac464SStefano Babic case fpga_lattice: 280439f6f7eSWolfgang Denk #if defined(CONFIG_FPGA_LATTICE) 2813b8ac464SStefano Babic ret_val = lattice_dump(desc->devdesc, buf, bsize); 282439f6f7eSWolfgang Denk #else 283f6555d90SMichal Simek fpga_no_sup((char *)__func__, "Lattice devices"); 284439f6f7eSWolfgang Denk #endif 2853b8ac464SStefano Babic break; 286c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 287c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf("%s: Invalid or unsupported device type %d\n", 288f6555d90SMichal Simek __func__, desc->devtype); 289c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 290c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 291c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 292c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 293c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 294c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 295f6555d90SMichal Simek /* 296f6555d90SMichal Simek * fpga_info 297c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * front end to fpga_dev_info. If devnum is invalid, report on all 298c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * available devices. 299c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 300c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int fpga_info(int devnum) 301c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 302c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (devnum == FPGA_INVALID_DEVICE) { 303c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (next_desc > 0) { 304c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int dev; 305c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 306f6555d90SMichal Simek for (dev = 0; dev < next_desc; dev++) 307c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fpga_dev_info(dev); 308f6555d90SMichal Simek 309c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return FPGA_SUCCESS; 310c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 311f6555d90SMichal Simek printf("%s: No FPGA devices available.\n", __func__); 312c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return FPGA_FAIL; 313c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 314c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 315c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 316f6555d90SMichal Simek return fpga_dev_info(devnum); 317f6555d90SMichal Simek } 318