xref: /rk3399_rockchip-uboot/drivers/fpga/altera.c (revision fda915a4cf171f4ef3077adbc7bc1680a140b0d6)
1c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /*
2c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2003
3c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
4c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  *
5c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2002
6c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  *
81a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
9c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  */
10c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
11c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /*
12c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  *  Altera FPGA support
13c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  */
14c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
15*fda915a4SMarek Vasut #include <errno.h>
16c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <ACEX1K.h>
17c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <stratixII.h>
18c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
190ae16cbbSMarek Vasut /* Define FPGA_DEBUG to 1 to get debug printf's */
200ae16cbbSMarek Vasut #define FPGA_DEBUG	0
21c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
2254c96b18SMarek Vasut static int altera_validate(Altera_desc *desc, const char *fn)
2354c96b18SMarek Vasut {
2454c96b18SMarek Vasut 	if (!desc) {
2554c96b18SMarek Vasut 		printf("%s: NULL descriptor!\n", fn);
26*fda915a4SMarek Vasut 		return -EINVAL;
2754c96b18SMarek Vasut 	}
2854c96b18SMarek Vasut 
2954c96b18SMarek Vasut 	if ((desc->family < min_altera_type) ||
3054c96b18SMarek Vasut 	    (desc->family > max_altera_type)) {
3154c96b18SMarek Vasut 		printf("%s: Invalid family type, %d\n", fn, desc->family);
32*fda915a4SMarek Vasut 		return -EINVAL;
3354c96b18SMarek Vasut 	}
3454c96b18SMarek Vasut 
3554c96b18SMarek Vasut 	if ((desc->iface < min_altera_iface_type) ||
3654c96b18SMarek Vasut 	    (desc->iface > max_altera_iface_type)) {
3754c96b18SMarek Vasut 		printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
38*fda915a4SMarek Vasut 		return -EINVAL;
3954c96b18SMarek Vasut 	}
4054c96b18SMarek Vasut 
4154c96b18SMarek Vasut 	if (!desc->size) {
4254c96b18SMarek Vasut 		printf("%s: NULL part size\n", fn);
43*fda915a4SMarek Vasut 		return -EINVAL;
4454c96b18SMarek Vasut 	}
4554c96b18SMarek Vasut 
46*fda915a4SMarek Vasut 	return 0;
4754c96b18SMarek Vasut }
48c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
49c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
50e6a857daSWolfgang Denk int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
51c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
52c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	int ret_val = FPGA_FAIL;	/* assume a failure */
53c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
54*fda915a4SMarek Vasut 	if (altera_validate(desc, (char *)__func__)) {
550ae16cbbSMarek Vasut 		printf("%s: Invalid device descriptor\n", __func__);
564a4c0a5eSMarek Vasut 		return FPGA_FAIL;
574a4c0a5eSMarek Vasut 	}
584a4c0a5eSMarek Vasut 
59c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	switch (desc->family) {
60c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_ACEX1K:
61c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_CYC2:
62c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX1K)
630ae16cbbSMarek Vasut 		debug_cond(FPGA_DEBUG,
640ae16cbbSMarek Vasut 			   "%s: Launching the ACEX1K Loader...\n",
650ae16cbbSMarek Vasut 			   __func__);
66c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		ret_val = ACEX1K_load (desc, buf, bsize);
67c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_FPGA_CYCLON2)
680ae16cbbSMarek Vasut 		debug_cond(FPGA_DEBUG,
690ae16cbbSMarek Vasut 			   "%s: Launching the CYCLONE II Loader...\n",
700ae16cbbSMarek Vasut 			   __func__);
71c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		ret_val = CYC2_load (desc, buf, bsize);
72c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
73c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("%s: No support for ACEX1K devices.\n",
740ae16cbbSMarek Vasut 		       __func__);
75c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
76c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
77c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
78c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II)
79c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_StratixII:
800ae16cbbSMarek Vasut 		debug_cond(FPGA_DEBUG,
810ae16cbbSMarek Vasut 			   "%s: Launching the Stratix II Loader...\n",
820ae16cbbSMarek Vasut 			   __func__);
83c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		ret_val = StratixII_load (desc, buf, bsize);
84c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
85c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
86c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	default:
87c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("%s: Unsupported family type, %d\n",
880ae16cbbSMarek Vasut 		       __func__, desc->family);
89c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
90c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
91c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	return ret_val;
92c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
93c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
94e6a857daSWolfgang Denk int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
95c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
96c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	int ret_val = FPGA_FAIL;	/* assume a failure */
97c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
98*fda915a4SMarek Vasut 	if (altera_validate(desc, (char *)__func__)) {
990ae16cbbSMarek Vasut 		printf("%s: Invalid device descriptor\n", __func__);
1004a4c0a5eSMarek Vasut 		return FPGA_FAIL;
1014a4c0a5eSMarek Vasut 	}
1024a4c0a5eSMarek Vasut 
103c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	switch (desc->family) {
104c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_ACEX1K:
105c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX)
1060ae16cbbSMarek Vasut 		debug_cond(FPGA_DEBUG,
1070ae16cbbSMarek Vasut 			   "%s: Launching the ACEX1K Reader...\n",
1080ae16cbbSMarek Vasut 			   __func__);
109c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		ret_val = ACEX1K_dump (desc, buf, bsize);
110c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
111c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("%s: No support for ACEX1K devices.\n",
1120ae16cbbSMarek Vasut 		       __func__);
113c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
114c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
115c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
116c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II)
117c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_StratixII:
1180ae16cbbSMarek Vasut 		debug_cond(FPGA_DEBUG,
1190ae16cbbSMarek Vasut 			   "%s: Launching the Stratix II Reader...\n",
1200ae16cbbSMarek Vasut 			   __func__);
121c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		ret_val = StratixII_dump (desc, buf, bsize);
122c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
123c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
124c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	default:
125c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("%s: Unsupported family type, %d\n",
1260ae16cbbSMarek Vasut 		       __func__, desc->family);
127c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
128c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
129c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	return ret_val;
130c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
131c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
132c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int altera_info(Altera_desc *desc)
133c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
134c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	int ret_val = FPGA_FAIL;
135c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
136*fda915a4SMarek Vasut 	if (altera_validate (desc, (char *)__func__)) {
1374a4c0a5eSMarek Vasut 		printf("%s: Invalid device descriptor\n", __func__);
1384a4c0a5eSMarek Vasut 		return FPGA_FAIL;
1394a4c0a5eSMarek Vasut 	}
1404a4c0a5eSMarek Vasut 
141c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	printf("Family:        \t");
142c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	switch (desc->family) {
143c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_ACEX1K:
144c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("ACEX1K\n");
145c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
146c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_CYC2:
147c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("CYCLON II\n");
148c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
149c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case Altera_StratixII:
150c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Stratix II\n");
151c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
152c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		/* Add new family types here */
153c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	default:
154c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Unknown family type, %d\n", desc->family);
155c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
156c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
157c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	printf("Interface type:\t");
158c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	switch (desc->iface) {
159c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case passive_serial:
160c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Passive Serial (PS)\n");
161c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
162c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case passive_parallel_synchronous:
163c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Passive Parallel Synchronous (PPS)\n");
164c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
165c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case passive_parallel_asynchronous:
166c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Passive Parallel Asynchronous (PPA)\n");
167c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
168c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case passive_serial_asynchronous:
169c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Passive Serial Asynchronous (PSA)\n");
170c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
171c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case altera_jtag_mode:		/* Not used */
172c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("JTAG Mode\n");
173c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
174c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case fast_passive_parallel:
175c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Fast Passive Parallel (FPP)\n");
176c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
177c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	case fast_passive_parallel_security:
1784a4c0a5eSMarek Vasut 		printf("Fast Passive Parallel with Security (FPPS)\n");
179c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		break;
180c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		/* Add new interface types here */
181c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	default:
182c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Unsupported interface type, %d\n", desc->iface);
183c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
184c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
185ddc94378SSimon Glass 	printf("Device Size:   \t%zd bytes\n"
186c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	       "Cookie:        \t0x%x (%d)\n",
187c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	       desc->size, desc->cookie, desc->cookie);
188c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
189c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	if (desc->iface_fns) {
190c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Device Function Table @ 0x%p\n", desc->iface_fns);
191c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		switch (desc->family) {
192c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_ACEX1K:
193c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_CYC2:
194c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX1K)
195c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			ACEX1K_info(desc);
196c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_FPGA_CYCLON2)
197c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			CYC2_info(desc);
198c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
199c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			/* just in case */
200c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("%s: No support for ACEX1K devices.\n",
2010ae16cbbSMarek Vasut 					__func__);
202c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
203c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
204c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II)
205c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_StratixII:
206c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			StratixII_info(desc);
207c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
208c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
209c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			/* Add new family types here */
210c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		default:
211c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			/* we don't need a message here - we give one up above */
212c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
213c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		}
214c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	} else {
215c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("No Device Function Table.\n");
216c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
217c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
218c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	ret_val = FPGA_SUCCESS;
219c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
220c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	return ret_val;
221c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
222