1*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 2*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2003 3*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de 4*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 5*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2002 6*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 7*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 8*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * See file CREDITS for list of people who contributed to this 9*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * project. 10*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 11*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * This program is free software; you can redistribute it and/or 12*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * modify it under the terms of the GNU General Public License as 13*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * published by the Free Software Foundation; either version 2 of 14*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * the License, or (at your option) any later version. 15*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 16*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * This program is distributed in the hope that it will be useful, 17*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * but WITHOUT ANY WARRANTY; without even the implied warranty of 18*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * GNU General Public License for more details. 20*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 21*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * You should have received a copy of the GNU General Public License 22*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * along with this program; if not, write to the Free Software 23*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * MA 02111-1307 USA 25*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * 26*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 27*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 28*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* 29*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD * Altera FPGA support 30*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD */ 31*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <common.h> 32*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <ACEX1K.h> 33*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <stratixII.h> 34*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 35*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Define FPGA_DEBUG to get debug printf's */ 36*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* #define FPGA_DEBUG */ 37*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 38*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #ifdef FPGA_DEBUG 39*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define PRINTF(fmt,args...) printf (fmt ,##args) 40*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 41*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #define PRINTF(fmt,args...) 42*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 43*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 44*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local Static Functions */ 45*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int altera_validate (Altera_desc * desc, const char *fn); 46*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 47*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */ 48*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int altera_load( Altera_desc *desc, void *buf, size_t bsize ) 49*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 50*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume a failure */ 51*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 52*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!altera_validate (desc, (char *)__FUNCTION__)) { 53*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid device descriptor\n", __FUNCTION__); 54*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 55*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 56*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_ACEX1K: 57*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_CYC2: 58*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX1K) 59*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the ACEX1K Loader...\n", 60*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 61*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = ACEX1K_load (desc, buf, bsize); 62*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_FPGA_CYCLON2) 63*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the CYCLON II Loader...\n", 64*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 65*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = CYC2_load (desc, buf, bsize); 66*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 67*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for ACEX1K devices.\n", 68*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 69*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 70*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 71*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 72*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II) 73*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_StratixII: 74*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Stratix II Loader...\n", 75*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 76*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = StratixII_load (desc, buf, bsize); 77*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 78*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 79*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 80*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Unsupported family type, %d\n", 81*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__, desc->family); 82*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 83*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 84*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 85*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 86*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 87*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 88*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int altera_dump( Altera_desc *desc, void *buf, size_t bsize ) 89*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 90*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume a failure */ 91*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 92*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!altera_validate (desc, (char *)__FUNCTION__)) { 93*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid device descriptor\n", __FUNCTION__); 94*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 95*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 96*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_ACEX1K: 97*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX) 98*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the ACEX1K Reader...\n", 99*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 100*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = ACEX1K_dump (desc, buf, bsize); 101*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 102*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for ACEX1K devices.\n", 103*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 104*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 105*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 106*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 107*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II) 108*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_StratixII: 109*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD PRINTF ("%s: Launching the Stratix II Reader...\n", 110*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 111*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = StratixII_dump (desc, buf, bsize); 112*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 113*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 114*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 115*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Unsupported family type, %d\n", 116*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__, desc->family); 117*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 118*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 119*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 120*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 121*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 122*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 123*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int altera_info( Altera_desc *desc ) 124*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 125*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; 126*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 127*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (altera_validate (desc, (char *)__FUNCTION__)) { 128*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Family: \t"); 129*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 130*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_ACEX1K: 131*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("ACEX1K\n"); 132*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 133*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_CYC2: 134*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("CYCLON II\n"); 135*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 136*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_StratixII: 137*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Stratix II\n"); 138*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 139*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Add new family types here */ 140*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 141*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Unknown family type, %d\n", desc->family); 142*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 143*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 144*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Interface type:\t"); 145*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->iface) { 146*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case passive_serial: 147*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Passive Serial (PS)\n"); 148*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 149*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case passive_parallel_synchronous: 150*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Passive Parallel Synchronous (PPS)\n"); 151*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 152*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case passive_parallel_asynchronous: 153*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Passive Parallel Asynchronous (PPA)\n"); 154*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 155*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case passive_serial_asynchronous: 156*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Passive Serial Asynchronous (PSA)\n"); 157*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 158*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case altera_jtag_mode: /* Not used */ 159*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("JTAG Mode\n"); 160*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 161*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fast_passive_parallel: 162*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Fast Passive Parallel (FPP)\n"); 163*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 164*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case fast_passive_parallel_security: 165*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf 166*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ("Fast Passive Parallel with Security (FPPS) \n"); 167*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 168*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Add new interface types here */ 169*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 170*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Unsupported interface type, %d\n", desc->iface); 171*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 172*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 173*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Device Size: \t%d bytes\n" 174*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD "Cookie: \t0x%x (%d)\n", 175*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD desc->size, desc->cookie, desc->cookie); 176*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 177*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc->iface_fns) { 178*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("Device Function Table @ 0x%p\n", desc->iface_fns); 179*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 180*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_ACEX1K: 181*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_CYC2: 182*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX1K) 183*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ACEX1K_info (desc); 184*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_FPGA_CYCLON2) 185*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD CYC2_info (desc); 186*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 187*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* just in case */ 188*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for ACEX1K devices.\n", 189*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 190*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 191*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 192*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II) 193*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_StratixII: 194*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD StratixII_info (desc); 195*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 196*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 197*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Add new family types here */ 198*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 199*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* we don't need a message here - we give one up above */ 200*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 201*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 202*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 203*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("No Device Function Table.\n"); 204*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 205*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 206*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = FPGA_SUCCESS; 207*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 208*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid device descriptor\n", __FUNCTION__); 209*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 210*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 211*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 212*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 213*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 214*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int altera_reloc( Altera_desc *desc, ulong reloc_offset) 215*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 216*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FPGA_FAIL; /* assume a failure */ 217*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 218*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (!altera_validate (desc, (char *)__FUNCTION__)) { 219*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid device descriptor\n", __FUNCTION__); 220*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 221*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD switch (desc->family) { 222*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_ACEX1K: 223*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX1K) 224*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = ACEX1K_reloc (desc, reloc_offset); 225*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 226*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for ACEX devices.\n", 227*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 228*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 229*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 230*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II) 231*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_StratixII: 232*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = StratixII_reloc (desc, reloc_offset); 233*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 234*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 235*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD case Altera_CYC2: 236*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_CYCLON2) 237*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = CYC2_reloc (desc, reloc_offset); 238*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else 239*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: No support for CYCLON II devices.\n", 240*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__); 241*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif 242*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD break; 243*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Add new family types here */ 244*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD default: 245*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Unsupported family type, %d\n", 246*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD __FUNCTION__, desc->family); 247*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 248*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 249*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 250*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 251*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 252*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 253*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */ 254*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 255*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int altera_validate (Altera_desc * desc, const char *fn) 256*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD { 257*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int ret_val = FALSE; 258*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 259*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc) { 260*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if ((desc->family > min_altera_type) && 261*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD (desc->family < max_altera_type)) { 262*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if ((desc->iface > min_altera_iface_type) && 263*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD (desc->iface < max_altera_iface_type)) { 264*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD if (desc->size) { 265*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD ret_val = TRUE; 266*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 267*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: NULL part size\n", fn); 268*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 269*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 270*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid Interface type, %d\n", 271*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD fn, desc->iface); 272*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 273*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 274*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: Invalid family type, %d\n", fn, desc->family); 275*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 276*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } else { 277*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD printf ("%s: NULL descriptor!\n", fn); 278*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 279*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 280*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD return ret_val; 281*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD } 282*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 283*c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */ 284