xref: /rk3399_rockchip-uboot/drivers/fpga/altera.c (revision 5561a841487fa246ebc6df17bed8eabfa33f3557)
1c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /*
2c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2003
3c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
4c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  *
5c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * (C) Copyright 2002
6c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  *
81a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
9c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  */
10c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
11c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /*
12c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  *  Altera FPGA support
13c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD  */
14c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
15c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <ACEX1K.h>
16c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #include <stratixII.h>
17c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
180ae16cbbSMarek Vasut /* Define FPGA_DEBUG to 1 to get debug printf's */
190ae16cbbSMarek Vasut #define FPGA_DEBUG	0
20c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
21c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* Local Static Functions */
22c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int altera_validate (Altera_desc * desc, const char *fn);
23c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
24c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
25e6a857daSWolfgang Denk int altera_load(Altera_desc *desc, const void *buf, size_t bsize)
26c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
27c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	int ret_val = FPGA_FAIL;	/* assume a failure */
28c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
290ae16cbbSMarek Vasut 	if (!altera_validate (desc, (char *)__func__)) {
300ae16cbbSMarek Vasut 		printf("%s: Invalid device descriptor\n", __func__);
31c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	} else {
32c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		switch (desc->family) {
33c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_ACEX1K:
34c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_CYC2:
35c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX1K)
360ae16cbbSMarek Vasut 			debug_cond(FPGA_DEBUG,
370ae16cbbSMarek Vasut 				   "%s: Launching the ACEX1K Loader...\n",
380ae16cbbSMarek Vasut 				   __func__);
39c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			ret_val = ACEX1K_load (desc, buf, bsize);
40c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_FPGA_CYCLON2)
410ae16cbbSMarek Vasut 			debug_cond(FPGA_DEBUG,
420ae16cbbSMarek Vasut 				   "%s: Launching the CYCLONE II Loader...\n",
430ae16cbbSMarek Vasut 				   __func__);
44c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			ret_val = CYC2_load (desc, buf, bsize);
45c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
46c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("%s: No support for ACEX1K devices.\n",
470ae16cbbSMarek Vasut 			       __func__);
48c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
49c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
50c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
51c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II)
52c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_StratixII:
530ae16cbbSMarek Vasut 			debug_cond(FPGA_DEBUG,
540ae16cbbSMarek Vasut 				   "%s: Launching the Stratix II Loader...\n",
550ae16cbbSMarek Vasut 				   __func__);
56c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			ret_val = StratixII_load (desc, buf, bsize);
57c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
58c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
59c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		default:
60c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("%s: Unsupported family type, %d\n",
610ae16cbbSMarek Vasut 			       __func__, desc->family);
62c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		}
63c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
64c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
65c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	return ret_val;
66c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
67c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
68e6a857daSWolfgang Denk int altera_dump(Altera_desc *desc, const void *buf, size_t bsize)
69c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
70c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	int ret_val = FPGA_FAIL;	/* assume a failure */
71c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
720ae16cbbSMarek Vasut 	if (!altera_validate (desc, (char *)__func__)) {
730ae16cbbSMarek Vasut 		printf("%s: Invalid device descriptor\n", __func__);
74c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	} else {
75c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		switch (desc->family) {
76c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_ACEX1K:
77c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX)
780ae16cbbSMarek Vasut 			debug_cond(FPGA_DEBUG,
790ae16cbbSMarek Vasut 				   "%s: Launching the ACEX1K Reader...\n",
800ae16cbbSMarek Vasut 				   __func__);
81c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			ret_val = ACEX1K_dump (desc, buf, bsize);
82c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
83c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("%s: No support for ACEX1K devices.\n",
840ae16cbbSMarek Vasut 			       __func__);
85c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
86c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
87c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
88c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II)
89c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_StratixII:
900ae16cbbSMarek Vasut 			debug_cond(FPGA_DEBUG,
910ae16cbbSMarek Vasut 				   "%s: Launching the Stratix II Reader...\n",
920ae16cbbSMarek Vasut 				   __func__);
93c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			ret_val = StratixII_dump (desc, buf, bsize);
94c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
95c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
96c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		default:
97c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("%s: Unsupported family type, %d\n",
980ae16cbbSMarek Vasut 			       __func__, desc->family);
99c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		}
100c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
101c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
102c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	return ret_val;
103c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
104c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
105c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD int altera_info( Altera_desc *desc )
106c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
107c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	int ret_val = FPGA_FAIL;
108c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
1090ae16cbbSMarek Vasut 	if (altera_validate (desc, (char *)__func__)) {
110c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Family:        \t");
111c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		switch (desc->family) {
112c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_ACEX1K:
113c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("ACEX1K\n");
114c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
115c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_CYC2:
116c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("CYCLON II\n");
117c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
118c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case Altera_StratixII:
119c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Stratix II\n");
120c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
121c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			/* Add new family types here */
122c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		default:
123c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Unknown family type, %d\n", desc->family);
124c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		}
125c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
126c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("Interface type:\t");
127c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		switch (desc->iface) {
128c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case passive_serial:
129c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Passive Serial (PS)\n");
130c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
131c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case passive_parallel_synchronous:
132c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Passive Parallel Synchronous (PPS)\n");
133c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
134c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case passive_parallel_asynchronous:
135c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Passive Parallel Asynchronous (PPA)\n");
136c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
137c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case passive_serial_asynchronous:
138c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Passive Serial Asynchronous (PSA)\n");
139c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
140c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case altera_jtag_mode:		/* Not used */
141c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("JTAG Mode\n");
142c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
143c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case fast_passive_parallel:
144c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Fast Passive Parallel (FPP)\n");
145c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
146c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		case fast_passive_parallel_security:
147c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf
148c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			    ("Fast Passive Parallel with Security (FPPS) \n");
149c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			break;
150c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			/* Add new interface types here */
151c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		default:
152c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Unsupported interface type, %d\n", desc->iface);
153c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		}
154c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
155ddc94378SSimon Glass 		printf("Device Size:   \t%zd bytes\n"
156c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		       "Cookie:        \t0x%x (%d)\n",
157c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		       desc->size, desc->cookie, desc->cookie);
158c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
159c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		if (desc->iface_fns) {
160c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("Device Function Table @ 0x%p\n", desc->iface_fns);
161c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			switch (desc->family) {
162c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			case Altera_ACEX1K:
163c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			case Altera_CYC2:
164c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_ACEX1K)
165c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				ACEX1K_info(desc);
166c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_FPGA_CYCLON2)
167c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				CYC2_info(desc);
168c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #else
169c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				/* just in case */
170c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				printf("%s: No support for ACEX1K devices.\n",
1710ae16cbbSMarek Vasut 						__func__);
172c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
173c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				break;
174c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_FPGA_STRATIX_II)
175c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			case Altera_StratixII:
176c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				StratixII_info(desc);
177c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				break;
178c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD #endif
179c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				/* Add new family types here */
180c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			default:
181c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				/* we don't need a message here - we give one up above */
182c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 				break;
183c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			}
184c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		} else {
185c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 			printf("No Device Function Table.\n");
186c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		}
187c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
188c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		ret_val = FPGA_SUCCESS;
189c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	} else {
1900ae16cbbSMarek Vasut 		printf("%s: Invalid device descriptor\n", __func__);
191c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
192c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
193c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	return ret_val;
194c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
195c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
196c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
197c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
198c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD static int altera_validate(Altera_desc *desc, const char *fn)
199c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD {
200*5561a841SMarek Vasut 	if (!desc) {
201c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 		printf("%s: NULL descriptor!\n", fn);
202*5561a841SMarek Vasut 		return false;
203c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 	}
204c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
205*5561a841SMarek Vasut 	if ((desc->family < min_altera_type) ||
206*5561a841SMarek Vasut 	    (desc->family > max_altera_type)) {
207*5561a841SMarek Vasut 		printf("%s: Invalid family type, %d\n", fn, desc->family);
208*5561a841SMarek Vasut 		return false;
209*5561a841SMarek Vasut 	}
210*5561a841SMarek Vasut 
211*5561a841SMarek Vasut 	if ((desc->iface < min_altera_iface_type) ||
212*5561a841SMarek Vasut 	    (desc->iface > max_altera_iface_type)) {
213*5561a841SMarek Vasut 		printf("%s: Invalid Interface type, %d\n", fn, desc->iface);
214*5561a841SMarek Vasut 		return false;
215*5561a841SMarek Vasut 	}
216*5561a841SMarek Vasut 
217*5561a841SMarek Vasut 	if (!desc->size) {
218*5561a841SMarek Vasut 		printf("%s: NULL part size\n", fn);
219*5561a841SMarek Vasut 		return false;
220*5561a841SMarek Vasut 	}
221*5561a841SMarek Vasut 
222*5561a841SMarek Vasut 	return true;
223c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD }
224c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD 
225c8aa7dfcSJean-Christophe PLAGNIOL-VILLARD /* ------------------------------------------------------------------------- */
226