xref: /rk3399_rockchip-uboot/drivers/ddr/marvell/axp/ddr3_axp_mc_static.h (revision f46c25583a73042edf432b209ee4b93bc3f7e762) 
1ff9112dfSStefan Roese /*
2ff9112dfSStefan Roese  * Copyright (C) Marvell International Ltd. and its affiliates
3ff9112dfSStefan Roese  *
4ff9112dfSStefan Roese  * SPDX-License-Identifier:	GPL-2.0
5ff9112dfSStefan Roese  */
6ff9112dfSStefan Roese 
7ff9112dfSStefan Roese #ifndef __AXP_MC_STATIC_H
8ff9112dfSStefan Roese #define __AXP_MC_STATIC_H
9ff9112dfSStefan Roese 
10ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
11*4444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
12ff9112dfSStefan Roese 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
13*4444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
14ff9112dfSStefan Roese 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
15ff9112dfSStefan Roese #endif
16ff9112dfSStefan Roese 	{0x00001404, 0x3630b800},	/*Dunit Control Low Register */
17ff9112dfSStefan Roese 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
18ff9112dfSStefan Roese 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
19ff9112dfSStefan Roese 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
20ff9112dfSStefan Roese 
21ff9112dfSStefan Roese #ifdef DB_78X60_PCAC
22ff9112dfSStefan Roese 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
23ff9112dfSStefan Roese #else
24ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
25ff9112dfSStefan Roese #endif
26ff9112dfSStefan Roese 
27ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
28ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
29ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
30ff9112dfSStefan Roese 	{0x00001424, 0x0000D3FF},	/*Dunit Control High Register */
31ff9112dfSStefan Roese 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
32ff9112dfSStefan Roese 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
33ff9112dfSStefan Roese 	{0x0000147C, 0x0000c671},
34ff9112dfSStefan Roese 
35ff9112dfSStefan Roese 	{0x000014a0, 0x000002A9},
36ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
37ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
38ff9112dfSStefan Roese 
39ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
40ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
41ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
42ff9112dfSStefan Roese 
43ff9112dfSStefan Roese 	{0x000014C0, 0x192434e9},	/* DRAM address and Control Driving Strenght  */
44ff9112dfSStefan Roese 	{0x000014C4, 0x092434e9},	/* DRAM Data and DQS Driving Strenght  */
45ff9112dfSStefan Roese 
46ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
47ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
48ff9112dfSStefan Roese 
49ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
50ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
51ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
52ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
53ff9112dfSStefan Roese 
54ff9112dfSStefan Roese 	/*     {0x00001524, 0x0000C800},  */
55ff9112dfSStefan Roese 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
56ff9112dfSStefan Roese 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
57ff9112dfSStefan Roese 
58ff9112dfSStefan Roese 	{0x000015D0, 0x00000640},	/*MR0 */
59ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
60ff9112dfSStefan Roese 	{0x000015D8, 0x00000010},	/*MR2 */
61ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
62ff9112dfSStefan Roese 
63ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
64ff9112dfSStefan Roese 	{0x000015EC, 0xd800aa25},	/*DDR PHY */
65ff9112dfSStefan Roese 	{0x0, 0x0}
66ff9112dfSStefan Roese };
67ff9112dfSStefan Roese 
68ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = {
69*4444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
70ff9112dfSStefan Roese 	{0x00001400, 0x7301c924},	/*DDR SDRAM Configuration Register */
71*4444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
72ff9112dfSStefan Roese 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
73ff9112dfSStefan Roese #endif
74ff9112dfSStefan Roese 	{0x00001404, 0x3630b800},	/*Dunit Control Low Register */
75ff9112dfSStefan Roese 	{0x00001408, 0x43149775},	/*DDR SDRAM Timing (Low) Register */
76ff9112dfSStefan Roese 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
77ff9112dfSStefan Roese 	{0x0000140C, 0x38d83fe0},	/*DDR SDRAM Timing (High) Register */
78ff9112dfSStefan Roese 
79ff9112dfSStefan Roese #ifdef DB_78X60_PCAC
80ff9112dfSStefan Roese 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
81ff9112dfSStefan Roese #else
82ff9112dfSStefan Roese 	{0x00001410, 0x040F000C},	/*DDR SDRAM Open Pages Control Register */
83ff9112dfSStefan Roese #endif
84ff9112dfSStefan Roese 
85ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
86ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
87ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
88ff9112dfSStefan Roese 	{0x00001424, 0x0000D3FF},	/*Dunit Control High Register */
89ff9112dfSStefan Roese 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
90ff9112dfSStefan Roese 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
91ff9112dfSStefan Roese 	{0x0000147C, 0x0000c671},
92ff9112dfSStefan Roese 
93ff9112dfSStefan Roese 	{0x000014a0, 0x000002A9},
94ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
95ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
96ff9112dfSStefan Roese 
97ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
98ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
99ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
100ff9112dfSStefan Roese 
101ff9112dfSStefan Roese 	{0x000014C0, 0x192434e9},	/* DRAM address and Control Driving Strenght  */
102ff9112dfSStefan Roese 	{0x000014C4, 0x092434e9},	/* DRAM Data and DQS Driving Strenght  */
103ff9112dfSStefan Roese 
104ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
105ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
106ff9112dfSStefan Roese 
107ff9112dfSStefan Roese 	{0x0001504, 0x3FFFFFF1},	/* CS0 Size */
108ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
109ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
110ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
111ff9112dfSStefan Roese 
112ff9112dfSStefan Roese 	/*     {0x00001524, 0x0000C800},  */
113ff9112dfSStefan Roese 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
114ff9112dfSStefan Roese 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
115ff9112dfSStefan Roese 
116ff9112dfSStefan Roese 	{0x000015D0, 0x00000640},	/*MR0 */
117ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
118ff9112dfSStefan Roese 	{0x000015D8, 0x00000010},	/*MR2 */
119ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
120ff9112dfSStefan Roese 
121ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
122ff9112dfSStefan Roese 	{0x000015EC, 0xd800aa25},	/*DDR PHY */
123ff9112dfSStefan Roese 	{0x0, 0x0}
124ff9112dfSStefan Roese };
125ff9112dfSStefan Roese 
126ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
127*4444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
128ff9112dfSStefan Roese 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
129*4444d230SPhil Sutter #else /* CONFIG_DDR_64BIT */
130ff9112dfSStefan Roese 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
131ff9112dfSStefan Roese #endif
132ff9112dfSStefan Roese 	{0x00001404, 0x3630B840},	/*Dunit Control Low Register */
133ff9112dfSStefan Roese 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
134ff9112dfSStefan Roese 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
135ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
136ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
137ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
138ff9112dfSStefan Roese 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
139ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
140ff9112dfSStefan Roese 	{0x00001424, 0x0100D3FF},	/*Dunit Control High Register */
141ff9112dfSStefan Roese 	{0x00001428, 0x000D6720},	/*Dunit Control High Register */
142ff9112dfSStefan Roese 	{0x0000142C, 0x014C2F38},	/*Dunit Control High Register */
143ff9112dfSStefan Roese 	{0x0000147C, 0x00006571},
144ff9112dfSStefan Roese 
145ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
146ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
147ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
148ff9112dfSStefan Roese 
149ff9112dfSStefan Roese 	{0x000014a0, 0x000002A9},
150ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
151ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
152ff9112dfSStefan Roese 
153ff9112dfSStefan Roese 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
154ff9112dfSStefan Roese 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
155ff9112dfSStefan Roese 
156ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
157ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
158ff9112dfSStefan Roese 
159ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
160ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
161ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
162ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
163ff9112dfSStefan Roese 
164ff9112dfSStefan Roese 	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
165ff9112dfSStefan Roese 	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
166ff9112dfSStefan Roese 
167ff9112dfSStefan Roese 	{0x000015D0, 0x00000630},	/*MR0 */
168ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
169ff9112dfSStefan Roese 	{0x000015D8, 0x00000008},	/*MR2 */
170ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
171ff9112dfSStefan Roese 
172ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQDS Configuration Register */
173ff9112dfSStefan Roese 	/* {0x000015EC, 0xDE000025}, *//*DDR PHY */
174ff9112dfSStefan Roese 	{0x000015EC, 0xF800AA25},	/*DDR PHY */
175ff9112dfSStefan Roese 	{0x0, 0x0}
176ff9112dfSStefan Roese };
177ff9112dfSStefan Roese 
178ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
179*4444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
180ff9112dfSStefan Roese 	{0x00001400, 0x73014A28},	/*DDR SDRAM Configuration Register */
181*4444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
182ff9112dfSStefan Roese 	{0x00001400, 0x7301CA28},	/*DDR SDRAM Configuration Register */
183ff9112dfSStefan Roese #endif
184ff9112dfSStefan Roese 	{0x00001404, 0x3630B040},	/*Dunit Control Low Register */
185ff9112dfSStefan Roese 	{0x00001408, 0x44149887},	/*DDR SDRAM Timing (Low) Register */
186ff9112dfSStefan Roese 	/* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */
187ff9112dfSStefan Roese 	{0x0000140C, 0x38D83FE0},	/*DDR SDRAM Timing (High) Register */
188ff9112dfSStefan Roese 
189ff9112dfSStefan Roese #ifdef DB_78X60_PCAC
190ff9112dfSStefan Roese 	{0x00001410, 0x040F0001},	/*DDR SDRAM Address Control Register */
191ff9112dfSStefan Roese #else
192ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Open Pages Control Register */
193ff9112dfSStefan Roese #endif
194ff9112dfSStefan Roese 
195ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
196ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
197ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
198ff9112dfSStefan Roese 	{0x00001424, 0x0100D1FF},	/*Dunit Control High Register */
199ff9112dfSStefan Roese 	{0x00001428, 0x000F8830},	/*Dunit Control High Register */
200ff9112dfSStefan Roese 	{0x0000142C, 0x214C2F38},	/*Dunit Control High Register */
201ff9112dfSStefan Roese 	{0x0000147C, 0x0000c671},
202ff9112dfSStefan Roese 
203ff9112dfSStefan Roese 	{0x000014a8, 0x00000101},	/*2:1 */
204ff9112dfSStefan Roese 	{0x00020220, 0x00000007},
205ff9112dfSStefan Roese 
206ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
207ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
208ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
209ff9112dfSStefan Roese 
210ff9112dfSStefan Roese 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
211ff9112dfSStefan Roese 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
212ff9112dfSStefan Roese 
213ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
214ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
215ff9112dfSStefan Roese 
216ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
217ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
218ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
219ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
220ff9112dfSStefan Roese 
221ff9112dfSStefan Roese 	/*     {0x00001524, 0x0000C800},  */
222ff9112dfSStefan Roese 	{0x00001538, 0x0000000b},	/*Read Data Sample Delays Register */
223ff9112dfSStefan Roese 	{0x0000153C, 0x0000000d},	/*Read Data Ready Delay Register */
224ff9112dfSStefan Roese 
225ff9112dfSStefan Roese 	{0x000015D0, 0x00000650},	/*MR0 */
226ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
227ff9112dfSStefan Roese 	{0x000015D8, 0x00000010},	/*MR2 */
228ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
229ff9112dfSStefan Roese 
230ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQC Configuration Register */
231ff9112dfSStefan Roese 	{0x000015EC, 0xDE000025},	/*DDR PHY */
232ff9112dfSStefan Roese 	{0x0, 0x0}
233ff9112dfSStefan Roese };
234ff9112dfSStefan Roese 
235ff9112dfSStefan Roese MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = {
236*4444d230SPhil Sutter #ifdef CONFIG_DDR_32BIT
237ff9112dfSStefan Roese 	{0x00001400, 0x73004C30},	/*DDR SDRAM Configuration Register */
238*4444d230SPhil Sutter #else /*CONFIG_DDR_64BIT */
239ff9112dfSStefan Roese 	{0x00001400, 0x7300CC30},	/*DDR SDRAM Configuration Register */
240ff9112dfSStefan Roese 	/*{0x00001400, 0x7304CC30},  *//*DDR SDRAM Configuration Register */
241ff9112dfSStefan Roese #endif
242ff9112dfSStefan Roese 	{0x00001404, 0x3630B840},	/*Dunit Control Low Register */
243ff9112dfSStefan Roese 	{0x00001408, 0x33137663},	/*DDR SDRAM Timing (Low) Register */
244ff9112dfSStefan Roese 	{0x0000140C, 0x38000C55},	/*DDR SDRAM Timing (High) Register */
245ff9112dfSStefan Roese 	{0x00001410, 0x040F0000},	/*DDR SDRAM Address Control Register */
246ff9112dfSStefan Roese 	{0x00001414, 0x00000000},	/*DDR SDRAM Open Pages Control Register */
247ff9112dfSStefan Roese 	{0x00001418, 0x00000e00},	/*DDR SDRAM Operation Register */
248ff9112dfSStefan Roese 	{0x0000141C, 0x00000672},	/*DDR SDRAM Mode Register */
249ff9112dfSStefan Roese 	{0x00001420, 0x00000004},	/*DDR SDRAM Extended Mode Register */
250ff9112dfSStefan Roese 	{0x00001424, 0x0100F1FF},	/*Dunit Control High Register */
251ff9112dfSStefan Roese 	{0x00001428, 0x000D6720},	/*Dunit Control High Register */
252ff9112dfSStefan Roese 	{0x0000142C, 0x014C2F38},	/*Dunit Control High Register */
253ff9112dfSStefan Roese 	{0x0000147C, 0x00006571},
254ff9112dfSStefan Roese 
255ff9112dfSStefan Roese 	{0x00001494, 0x00010000},	/*DDR SDRAM ODT Control (Low) Register */
256ff9112dfSStefan Roese 	{0x00001498, 0x00000000},	/*DDR SDRAM ODT Control (High) Register */
257ff9112dfSStefan Roese 	{0x0000149C, 0x00000301},	/*DDR Dunit ODT Control Register */
258ff9112dfSStefan Roese 
259ff9112dfSStefan Roese 	{0x000014C0, 0x192424C8},	/* DRAM address and Control Driving Strenght  */
260ff9112dfSStefan Roese 	{0x000014C4, 0xEFB24C8},	/* DRAM Data and DQS Driving Strenght  */
261ff9112dfSStefan Roese 
262ff9112dfSStefan Roese 	{0x000200e8, 0x3FFF0E01},	/* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */
263ff9112dfSStefan Roese 	{0x00020184, 0x3FFFFFE0},	/* DO NOT Modify - Close fast path Window to - 2G */
264ff9112dfSStefan Roese 
265ff9112dfSStefan Roese 	{0x0001504, 0x7FFFFFF1},	/* CS0 Size */
266ff9112dfSStefan Roese 	{0x000150C, 0x00000000},	/* CS1 Size */
267ff9112dfSStefan Roese 	{0x0001514, 0x00000000},	/* CS2 Size */
268ff9112dfSStefan Roese 	{0x000151C, 0x00000000},	/* CS3 Size */
269ff9112dfSStefan Roese 
270ff9112dfSStefan Roese 	{0x00001538, 0x00000008},	/*Read Data Sample Delays Register */
271ff9112dfSStefan Roese 	{0x0000153C, 0x0000000A},	/*Read Data Ready Delay Register */
272ff9112dfSStefan Roese 
273ff9112dfSStefan Roese 	{0x000015D0, 0x00000630},	/*MR0 */
274ff9112dfSStefan Roese 	{0x000015D4, 0x00000046},	/*MR1 */
275ff9112dfSStefan Roese 	{0x000015D8, 0x00000008},	/*MR2 */
276ff9112dfSStefan Roese 	{0x000015DC, 0x00000000},	/*MR3 */
277ff9112dfSStefan Roese 
278ff9112dfSStefan Roese 	{0x000015E4, 0x00203c18},	/*ZQDS Configuration Register */
279ff9112dfSStefan Roese 	{0x000015EC, 0xDE000025},	/*DDR PHY */
280ff9112dfSStefan Roese 
281ff9112dfSStefan Roese 	{0x0, 0x0}
282ff9112dfSStefan Roese };
283ff9112dfSStefan Roese 
284ff9112dfSStefan Roese #endif /* __AXP_MC_STATIC_H */
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