xref: /rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/ddr_training_ip_db.h (revision 3c9cc70d7153da442575112d9a2643eecd17d534)
1*f1df9364SStefan Roese /*
2*f1df9364SStefan Roese  * Copyright (C) Marvell International Ltd. and its affiliates
3*f1df9364SStefan Roese  *
4*f1df9364SStefan Roese  * SPDX-License-Identifier:	GPL-2.0
5*f1df9364SStefan Roese  */
6*f1df9364SStefan Roese 
7*f1df9364SStefan Roese #ifndef _DDR_TRAINING_IP_DB_H_
8*f1df9364SStefan Roese #define _DDR_TRAINING_IP_DB_H_
9*f1df9364SStefan Roese 
10*f1df9364SStefan Roese #include "ddr_topology_def.h"
11*f1df9364SStefan Roese #include "ddr3_training_ip_db.h"
12*f1df9364SStefan Roese 
13*f1df9364SStefan Roese u32 speed_bin_table(u8 index, enum speed_bin_table_elements element);
14*f1df9364SStefan Roese u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index);
15*f1df9364SStefan Roese 
16*f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_DB_H_ */
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