xref: /rk3399_rockchip-uboot/drivers/ddr/marvell/a38x/ddr3_training_ip_db.h (revision 3c9cc70d7153da442575112d9a2643eecd17d534)
1*f1df9364SStefan Roese /*
2*f1df9364SStefan Roese  * Copyright (C) Marvell International Ltd. and its affiliates
3*f1df9364SStefan Roese  *
4*f1df9364SStefan Roese  * SPDX-License-Identifier:	GPL-2.0
5*f1df9364SStefan Roese  */
6*f1df9364SStefan Roese 
7*f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_DB_H_
8*f1df9364SStefan Roese #define _DDR3_TRAINING_IP_DB_H_
9*f1df9364SStefan Roese 
10*f1df9364SStefan Roese enum hws_pattern {
11*f1df9364SStefan Roese 	PATTERN_PBS1,
12*f1df9364SStefan Roese 	PATTERN_PBS2,
13*f1df9364SStefan Roese 	PATTERN_RL,
14*f1df9364SStefan Roese 	PATTERN_STATIC_PBS,
15*f1df9364SStefan Roese 	PATTERN_KILLER_DQ0,
16*f1df9364SStefan Roese 	PATTERN_KILLER_DQ1,
17*f1df9364SStefan Roese 	PATTERN_KILLER_DQ2,
18*f1df9364SStefan Roese 	PATTERN_KILLER_DQ3,
19*f1df9364SStefan Roese 	PATTERN_KILLER_DQ4,
20*f1df9364SStefan Roese 	PATTERN_KILLER_DQ5,
21*f1df9364SStefan Roese 	PATTERN_KILLER_DQ6,
22*f1df9364SStefan Roese 	PATTERN_KILLER_DQ7,
23*f1df9364SStefan Roese 	PATTERN_PBS3,
24*f1df9364SStefan Roese 	PATTERN_RL2,
25*f1df9364SStefan Roese 	PATTERN_TEST,
26*f1df9364SStefan Roese 	PATTERN_FULL_SSO0,
27*f1df9364SStefan Roese 	PATTERN_FULL_SSO1,
28*f1df9364SStefan Roese 	PATTERN_FULL_SSO2,
29*f1df9364SStefan Roese 	PATTERN_FULL_SSO3,
30*f1df9364SStefan Roese 	PATTERN_VREF,
31*f1df9364SStefan Roese 	PATTERN_LIMIT
32*f1df9364SStefan Roese };
33*f1df9364SStefan Roese 
34*f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_DB_H_ */
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