1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_TRAINING_IP_CENTRALIZATION_H 8*f1df9364SStefan Roese #define _DDR3_TRAINING_IP_CENTRALIZATION_H 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese int ddr3_tip_centralization_tx(u32 dev_num); 11*f1df9364SStefan Roese int ddr3_tip_centralization_rx(u32 dev_num); 12*f1df9364SStefan Roese int ddr3_tip_print_centralization_result(u32 dev_num); 13*f1df9364SStefan Roese int ddr3_tip_special_rx(u32 dev_num); 14*f1df9364SStefan Roese 15*f1df9364SStefan Roese #endif /* _DDR3_TRAINING_IP_CENTRALIZATION_H */ 16