1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_LOGGING_CONFIG_H 8*f1df9364SStefan Roese #define _DDR3_LOGGING_CONFIG_H 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #ifdef SILENT_LIB 11*f1df9364SStefan Roese #define DEBUG_TRAINING_BIST_ENGINE(level, s) 12*f1df9364SStefan Roese #define DEBUG_TRAINING_IP(level, s) 13*f1df9364SStefan Roese #define DEBUG_CENTRALIZATION_ENGINE(level, s) 14*f1df9364SStefan Roese #define DEBUG_TRAINING_HW_ALG(level, s) 15*f1df9364SStefan Roese #define DEBUG_TRAINING_IP_ENGINE(level, s) 16*f1df9364SStefan Roese #define DEBUG_LEVELING(level, s) 17*f1df9364SStefan Roese #define DEBUG_PBS_ENGINE(level, s) 18*f1df9364SStefan Roese #define DEBUG_TRAINING_STATIC_IP(level, s) 19*f1df9364SStefan Roese #define DEBUG_TRAINING_ACCESS(level, s) 20*f1df9364SStefan Roese #else 21*f1df9364SStefan Roese #ifdef LIB_FUNCTIONAL_DEBUG_ONLY 22*f1df9364SStefan Roese #define DEBUG_TRAINING_BIST_ENGINE(level, s) 23*f1df9364SStefan Roese #define DEBUG_TRAINING_IP_ENGINE(level, s) 24*f1df9364SStefan Roese #define DEBUG_TRAINING_IP(level, s) \ 25*f1df9364SStefan Roese if (level >= debug_training) \ 26*f1df9364SStefan Roese printf s 27*f1df9364SStefan Roese #define DEBUG_CENTRALIZATION_ENGINE(level, s) \ 28*f1df9364SStefan Roese if (level >= debug_centralization) \ 29*f1df9364SStefan Roese printf s 30*f1df9364SStefan Roese #define DEBUG_TRAINING_HW_ALG(level, s) \ 31*f1df9364SStefan Roese if (level >= debug_training_hw_alg) \ 32*f1df9364SStefan Roese printf s 33*f1df9364SStefan Roese #define DEBUG_LEVELING(level, s) \ 34*f1df9364SStefan Roese if (level >= debug_leveling) \ 35*f1df9364SStefan Roese printf s 36*f1df9364SStefan Roese #define DEBUG_PBS_ENGINE(level, s) \ 37*f1df9364SStefan Roese if (level >= debug_pbs) \ 38*f1df9364SStefan Roese printf s 39*f1df9364SStefan Roese #define DEBUG_TRAINING_STATIC_IP(level, s) \ 40*f1df9364SStefan Roese if (level >= debug_training_static) \ 41*f1df9364SStefan Roese printf s 42*f1df9364SStefan Roese #define DEBUG_TRAINING_ACCESS(level, s) \ 43*f1df9364SStefan Roese if (level >= debug_training_access) \ 44*f1df9364SStefan Roese printf s 45*f1df9364SStefan Roese #else 46*f1df9364SStefan Roese #define DEBUG_TRAINING_BIST_ENGINE(level, s) \ 47*f1df9364SStefan Roese if (level >= debug_training_bist) \ 48*f1df9364SStefan Roese printf s 49*f1df9364SStefan Roese 50*f1df9364SStefan Roese #define DEBUG_TRAINING_IP_ENGINE(level, s) \ 51*f1df9364SStefan Roese if (level >= debug_training_ip) \ 52*f1df9364SStefan Roese printf s 53*f1df9364SStefan Roese #define DEBUG_TRAINING_IP(level, s) \ 54*f1df9364SStefan Roese if (level >= debug_training) \ 55*f1df9364SStefan Roese printf s 56*f1df9364SStefan Roese #define DEBUG_CENTRALIZATION_ENGINE(level, s) \ 57*f1df9364SStefan Roese if (level >= debug_centralization) \ 58*f1df9364SStefan Roese printf s 59*f1df9364SStefan Roese #define DEBUG_TRAINING_HW_ALG(level, s) \ 60*f1df9364SStefan Roese if (level >= debug_training_hw_alg) \ 61*f1df9364SStefan Roese printf s 62*f1df9364SStefan Roese #define DEBUG_LEVELING(level, s) \ 63*f1df9364SStefan Roese if (level >= debug_leveling) \ 64*f1df9364SStefan Roese printf s 65*f1df9364SStefan Roese #define DEBUG_PBS_ENGINE(level, s) \ 66*f1df9364SStefan Roese if (level >= debug_pbs) \ 67*f1df9364SStefan Roese printf s 68*f1df9364SStefan Roese #define DEBUG_TRAINING_STATIC_IP(level, s) \ 69*f1df9364SStefan Roese if (level >= debug_training_static) \ 70*f1df9364SStefan Roese printf s 71*f1df9364SStefan Roese #define DEBUG_TRAINING_ACCESS(level, s) \ 72*f1df9364SStefan Roese if (level >= debug_training_access) \ 73*f1df9364SStefan Roese printf s 74*f1df9364SStefan Roese #endif 75*f1df9364SStefan Roese #endif 76*f1df9364SStefan Roese 77*f1df9364SStefan Roese /* Logging defines */ 78*f1df9364SStefan Roese #define DEBUG_LEVEL_TRACE 1 79*f1df9364SStefan Roese #define DEBUG_LEVEL_INFO 2 80*f1df9364SStefan Roese #define DEBUG_LEVEL_ERROR 3 81*f1df9364SStefan Roese 82*f1df9364SStefan Roese enum ddr_lib_debug_block { 83*f1df9364SStefan Roese DEBUG_BLOCK_STATIC, 84*f1df9364SStefan Roese DEBUG_BLOCK_TRAINING_MAIN, 85*f1df9364SStefan Roese DEBUG_BLOCK_LEVELING, 86*f1df9364SStefan Roese DEBUG_BLOCK_CENTRALIZATION, 87*f1df9364SStefan Roese DEBUG_BLOCK_PBS, 88*f1df9364SStefan Roese DEBUG_BLOCK_IP, 89*f1df9364SStefan Roese DEBUG_BLOCK_BIST, 90*f1df9364SStefan Roese DEBUG_BLOCK_ALG, 91*f1df9364SStefan Roese DEBUG_BLOCK_DEVICE, 92*f1df9364SStefan Roese DEBUG_BLOCK_ACCESS, 93*f1df9364SStefan Roese DEBUG_STAGES_REG_DUMP, 94*f1df9364SStefan Roese /* All excluding IP and REG_DUMP, should be enabled separatelly */ 95*f1df9364SStefan Roese DEBUG_BLOCK_ALL 96*f1df9364SStefan Roese }; 97*f1df9364SStefan Roese 98*f1df9364SStefan Roese int ddr3_tip_print_log(u32 dev_num, u32 mem_addr); 99*f1df9364SStefan Roese int ddr3_tip_print_stability_log(u32 dev_num); 100*f1df9364SStefan Roese 101*f1df9364SStefan Roese #endif /* _DDR3_LOGGING_CONFIG_H */ 102