1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_HWS_SIL_TRAINING_H 8*f1df9364SStefan Roese #define _DDR3_HWS_SIL_TRAINING_H 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #include "ddr3_training_ip.h" 11*f1df9364SStefan Roese #include "ddr3_training_ip_prv_if.h" 12*f1df9364SStefan Roese 13*f1df9364SStefan Roese int ddr3_silicon_pre_config(void); 14*f1df9364SStefan Roese int ddr3_silicon_init(void); 15*f1df9364SStefan Roese int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq); 16*f1df9364SStefan Roese 17*f1df9364SStefan Roese #endif /* _DDR3_HWS_SIL_TRAINING_H */ 18