1*f1df9364SStefan Roese /* 2*f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 3*f1df9364SStefan Roese * 4*f1df9364SStefan Roese * SPDX-License-Identifier: GPL-2.0 5*f1df9364SStefan Roese */ 6*f1df9364SStefan Roese 7*f1df9364SStefan Roese #ifndef _DDR3_A38X_H 8*f1df9364SStefan Roese #define _DDR3_A38X_H 9*f1df9364SStefan Roese 10*f1df9364SStefan Roese #define MAX_INTERFACE_NUM 1 11*f1df9364SStefan Roese #define MAX_BUS_NUM 5 12*f1df9364SStefan Roese 13*f1df9364SStefan Roese #include "ddr3_hws_hw_training_def.h" 14*f1df9364SStefan Roese 15*f1df9364SStefan Roese #define ECC_SUPPORT 16*f1df9364SStefan Roese 17*f1df9364SStefan Roese /* right now, we're not supporting this in mainline */ 18*f1df9364SStefan Roese #undef SUPPORT_STATIC_DUNIT_CONFIG 19*f1df9364SStefan Roese 20*f1df9364SStefan Roese /* Controler bus divider 1 for 32 bit, 2 for 64 bit */ 21*f1df9364SStefan Roese #define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1 22*f1df9364SStefan Roese 23*f1df9364SStefan Roese /* Tune internal training params values */ 24*f1df9364SStefan Roese #define TUNE_TRAINING_PARAMS_CK_DELAY 160 25*f1df9364SStefan Roese #define TUNE_TRAINING_PARAMS_CK_DELAY_16 160 26*f1df9364SStefan Roese #define TUNE_TRAINING_PARAMS_PFINGER 41 27*f1df9364SStefan Roese #define TUNE_TRAINING_PARAMS_NFINGER 43 28*f1df9364SStefan Roese #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xa 29*f1df9364SStefan Roese 30*f1df9364SStefan Roese #define MARVELL_BOARD MARVELL_BOARD_ID_BASE 31*f1df9364SStefan Roese 32*f1df9364SStefan Roese 33*f1df9364SStefan Roese #define REG_DEVICE_SAR1_ADDR 0xe4204 34*f1df9364SStefan Roese #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17 35*f1df9364SStefan Roese #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f 36*f1df9364SStefan Roese 37*f1df9364SStefan Roese /* DRAM Windows */ 38*f1df9364SStefan Roese #define REG_XBAR_WIN_5_CTRL_ADDR 0x20050 39*f1df9364SStefan Roese #define REG_XBAR_WIN_5_BASE_ADDR 0x20054 40*f1df9364SStefan Roese 41*f1df9364SStefan Roese /* DRAM Windows */ 42*f1df9364SStefan Roese #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040 43*f1df9364SStefan Roese #define REG_XBAR_WIN_4_BASE_ADDR 0x20044 44*f1df9364SStefan Roese #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048 45*f1df9364SStefan Roese #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078 46*f1df9364SStefan Roese #define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0 47*f1df9364SStefan Roese #define REG_XBAR_WIN_16_BASE_ADDR 0x200d4 48*f1df9364SStefan Roese #define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc 49*f1df9364SStefan Roese #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8 50*f1df9364SStefan Roese 51*f1df9364SStefan Roese #define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win)) 52*f1df9364SStefan Roese #define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win)) 53*f1df9364SStefan Roese 54*f1df9364SStefan Roese /* SatR defined too change topology busWidth and ECC configuration */ 55*f1df9364SStefan Roese #define DDR_SATR_CONFIG_MASK_WIDTH 0x8 56*f1df9364SStefan Roese #define DDR_SATR_CONFIG_MASK_ECC 0x10 57*f1df9364SStefan Roese #define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20 58*f1df9364SStefan Roese 59*f1df9364SStefan Roese #define REG_SAMPLE_RESET_HIGH_ADDR 0x18600 60*f1df9364SStefan Roese 61*f1df9364SStefan Roese #define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ 62*f1df9364SStefan Roese 63*f1df9364SStefan Roese /* Matrix enables DRAM modes (bus width/ECC) per boardId */ 64*f1df9364SStefan Roese #define TOPOLOGY_UPDATE_32BIT 0 65*f1df9364SStefan Roese #define TOPOLOGY_UPDATE_32BIT_ECC 1 66*f1df9364SStefan Roese #define TOPOLOGY_UPDATE_16BIT 2 67*f1df9364SStefan Roese #define TOPOLOGY_UPDATE_16BIT_ECC 3 68*f1df9364SStefan Roese #define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4 69*f1df9364SStefan Roese #define TOPOLOGY_UPDATE { \ 70*f1df9364SStefan Roese /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \ 71*f1df9364SStefan Roese {1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \ 72*f1df9364SStefan Roese {1, 1, 1, 1, 1}, /* DB_68XX_ID */ \ 73*f1df9364SStefan Roese {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \ 74*f1df9364SStefan Roese {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \ 75*f1df9364SStefan Roese {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \ 76*f1df9364SStefan Roese {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \ 77*f1df9364SStefan Roese {1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \ 78*f1df9364SStefan Roese }; 79*f1df9364SStefan Roese 80*f1df9364SStefan Roese enum { 81*f1df9364SStefan Roese CPU_1066MHZ_DDR_400MHZ, 82*f1df9364SStefan Roese CPU_RESERVED_DDR_RESERVED0, 83*f1df9364SStefan Roese CPU_667MHZ_DDR_667MHZ, 84*f1df9364SStefan Roese CPU_800MHZ_DDR_800MHZ, 85*f1df9364SStefan Roese CPU_RESERVED_DDR_RESERVED1, 86*f1df9364SStefan Roese CPU_RESERVED_DDR_RESERVED2, 87*f1df9364SStefan Roese CPU_RESERVED_DDR_RESERVED3, 88*f1df9364SStefan Roese LAST_FREQ 89*f1df9364SStefan Roese }; 90*f1df9364SStefan Roese 91*f1df9364SStefan Roese #define ACTIVE_INTERFACE_MASK 0x1 92*f1df9364SStefan Roese 93*f1df9364SStefan Roese #endif /* _DDR3_A38X_H */ 94