1 /* 2 * Copyright 2008-2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller. 9 * Based on code from spd_sdram.c 10 * Author: James Yang [at freescale.com] 11 */ 12 13 #include <common.h> 14 #include <fsl_ddr_sdram.h> 15 #include <fsl_errata.h> 16 #include <fsl_ddr.h> 17 #include <fsl_immap.h> 18 #include <asm/io.h> 19 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) 20 #include <asm/arch/clock.h> 21 #endif 22 23 /* 24 * Determine Rtt value. 25 * 26 * This should likely be either board or controller specific. 27 * 28 * Rtt(nominal) - DDR2: 29 * 0 = Rtt disabled 30 * 1 = 75 ohm 31 * 2 = 150 ohm 32 * 3 = 50 ohm 33 * Rtt(nominal) - DDR3: 34 * 0 = Rtt disabled 35 * 1 = 60 ohm 36 * 2 = 120 ohm 37 * 3 = 40 ohm 38 * 4 = 20 ohm 39 * 5 = 30 ohm 40 * 41 * FIXME: Apparently 8641 needs a value of 2 42 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572 43 * 44 * FIXME: There was some effort down this line earlier: 45 * 46 * unsigned int i; 47 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) { 48 * if (popts->dimmslot[i].num_valid_cs 49 * && (popts->cs_local_opts[2*i].odt_rd_cfg 50 * || popts->cs_local_opts[2*i].odt_wr_cfg)) { 51 * rtt = 2; 52 * break; 53 * } 54 * } 55 */ 56 static inline int fsl_ddr_get_rtt(void) 57 { 58 int rtt; 59 60 #if defined(CONFIG_SYS_FSL_DDR1) 61 rtt = 0; 62 #elif defined(CONFIG_SYS_FSL_DDR2) 63 rtt = 3; 64 #else 65 rtt = 0; 66 #endif 67 68 return rtt; 69 } 70 71 #ifdef CONFIG_SYS_FSL_DDR4 72 /* 73 * compute CAS write latency according to DDR4 spec 74 * CWL = 9 for <= 1600MT/s 75 * 10 for <= 1866MT/s 76 * 11 for <= 2133MT/s 77 * 12 for <= 2400MT/s 78 * 14 for <= 2667MT/s 79 * 16 for <= 2933MT/s 80 * 18 for higher 81 */ 82 static inline unsigned int compute_cas_write_latency( 83 const unsigned int ctrl_num) 84 { 85 unsigned int cwl; 86 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 87 if (mclk_ps >= 1250) 88 cwl = 9; 89 else if (mclk_ps >= 1070) 90 cwl = 10; 91 else if (mclk_ps >= 935) 92 cwl = 11; 93 else if (mclk_ps >= 833) 94 cwl = 12; 95 else if (mclk_ps >= 750) 96 cwl = 14; 97 else if (mclk_ps >= 681) 98 cwl = 16; 99 else 100 cwl = 18; 101 102 return cwl; 103 } 104 #else 105 /* 106 * compute the CAS write latency according to DDR3 spec 107 * CWL = 5 if tCK >= 2.5ns 108 * 6 if 2.5ns > tCK >= 1.875ns 109 * 7 if 1.875ns > tCK >= 1.5ns 110 * 8 if 1.5ns > tCK >= 1.25ns 111 * 9 if 1.25ns > tCK >= 1.07ns 112 * 10 if 1.07ns > tCK >= 0.935ns 113 * 11 if 0.935ns > tCK >= 0.833ns 114 * 12 if 0.833ns > tCK >= 0.75ns 115 */ 116 static inline unsigned int compute_cas_write_latency( 117 const unsigned int ctrl_num) 118 { 119 unsigned int cwl; 120 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 121 122 if (mclk_ps >= 2500) 123 cwl = 5; 124 else if (mclk_ps >= 1875) 125 cwl = 6; 126 else if (mclk_ps >= 1500) 127 cwl = 7; 128 else if (mclk_ps >= 1250) 129 cwl = 8; 130 else if (mclk_ps >= 1070) 131 cwl = 9; 132 else if (mclk_ps >= 935) 133 cwl = 10; 134 else if (mclk_ps >= 833) 135 cwl = 11; 136 else if (mclk_ps >= 750) 137 cwl = 12; 138 else { 139 cwl = 12; 140 printf("Warning: CWL is out of range\n"); 141 } 142 return cwl; 143 } 144 #endif 145 146 /* Chip Select Configuration (CSn_CONFIG) */ 147 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, 148 const memctl_options_t *popts, 149 const dimm_params_t *dimm_params) 150 { 151 unsigned int cs_n_en = 0; /* Chip Select enable */ 152 unsigned int intlv_en = 0; /* Memory controller interleave enable */ 153 unsigned int intlv_ctl = 0; /* Interleaving control */ 154 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */ 155 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */ 156 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */ 157 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */ 158 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */ 159 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */ 160 int go_config = 0; 161 #ifdef CONFIG_SYS_FSL_DDR4 162 unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */ 163 #else 164 unsigned int n_banks_per_sdram_device; 165 #endif 166 167 /* Compute CS_CONFIG only for existing ranks of each DIMM. */ 168 switch (i) { 169 case 0: 170 if (dimm_params[dimm_number].n_ranks > 0) { 171 go_config = 1; 172 /* These fields only available in CS0_CONFIG */ 173 if (!popts->memctl_interleaving) 174 break; 175 switch (popts->memctl_interleaving_mode) { 176 case FSL_DDR_256B_INTERLEAVING: 177 case FSL_DDR_CACHE_LINE_INTERLEAVING: 178 case FSL_DDR_PAGE_INTERLEAVING: 179 case FSL_DDR_BANK_INTERLEAVING: 180 case FSL_DDR_SUPERBANK_INTERLEAVING: 181 intlv_en = popts->memctl_interleaving; 182 intlv_ctl = popts->memctl_interleaving_mode; 183 break; 184 default: 185 break; 186 } 187 } 188 break; 189 case 1: 190 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \ 191 (dimm_number == 1 && dimm_params[1].n_ranks > 0)) 192 go_config = 1; 193 break; 194 case 2: 195 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \ 196 (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0)) 197 go_config = 1; 198 break; 199 case 3: 200 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \ 201 (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \ 202 (dimm_number == 3 && dimm_params[3].n_ranks > 0)) 203 go_config = 1; 204 break; 205 default: 206 break; 207 } 208 if (go_config) { 209 cs_n_en = 1; 210 ap_n_en = popts->cs_local_opts[i].auto_precharge; 211 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg; 212 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg; 213 #ifdef CONFIG_SYS_FSL_DDR4 214 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits; 215 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits; 216 #else 217 n_banks_per_sdram_device 218 = dimm_params[dimm_number].n_banks_per_sdram_device; 219 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2; 220 #endif 221 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12; 222 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8; 223 } 224 ddr->cs[i].config = (0 225 | ((cs_n_en & 0x1) << 31) 226 | ((intlv_en & 0x3) << 29) 227 | ((intlv_ctl & 0xf) << 24) 228 | ((ap_n_en & 0x1) << 23) 229 230 /* XXX: some implementation only have 1 bit starting at left */ 231 | ((odt_rd_cfg & 0x7) << 20) 232 233 /* XXX: Some implementation only have 1 bit starting at left */ 234 | ((odt_wr_cfg & 0x7) << 16) 235 236 | ((ba_bits_cs_n & 0x3) << 14) 237 | ((row_bits_cs_n & 0x7) << 8) 238 #ifdef CONFIG_SYS_FSL_DDR4 239 | ((bg_bits_cs_n & 0x3) << 4) 240 #endif 241 | ((col_bits_cs_n & 0x7) << 0) 242 ); 243 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config); 244 } 245 246 /* Chip Select Configuration 2 (CSn_CONFIG_2) */ 247 /* FIXME: 8572 */ 248 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) 249 { 250 unsigned int pasr_cfg = 0; /* Partial array self refresh config */ 251 252 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24); 253 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2); 254 } 255 256 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */ 257 258 #if !defined(CONFIG_SYS_FSL_DDR1) 259 /* 260 * Check DIMM configuration, return 2 if quad-rank or two dual-rank 261 * Return 1 if other two slots configuration. Return 0 if single slot. 262 */ 263 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) 264 { 265 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1 266 if (dimm_params[0].n_ranks == 4) 267 return 2; 268 #endif 269 270 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2 271 if ((dimm_params[0].n_ranks == 2) && 272 (dimm_params[1].n_ranks == 2)) 273 return 2; 274 275 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 276 if (dimm_params[0].n_ranks == 4) 277 return 2; 278 #endif 279 280 if ((dimm_params[0].n_ranks != 0) && 281 (dimm_params[2].n_ranks != 0)) 282 return 1; 283 #endif 284 return 0; 285 } 286 287 /* 288 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0) 289 * 290 * Avoid writing for DDR I. The new PQ38 DDR controller 291 * dreams up non-zero default values to be backwards compatible. 292 */ 293 static void set_timing_cfg_0(const unsigned int ctrl_num, 294 fsl_ddr_cfg_regs_t *ddr, 295 const memctl_options_t *popts, 296 const dimm_params_t *dimm_params) 297 { 298 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */ 299 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */ 300 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */ 301 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */ 302 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */ 303 304 /* Active powerdown exit timing (tXARD and tXARDS). */ 305 unsigned char act_pd_exit_mclk; 306 /* Precharge powerdown exit timing (tXP). */ 307 unsigned char pre_pd_exit_mclk; 308 /* ODT powerdown exit timing (tAXPD). */ 309 unsigned char taxpd_mclk = 0; 310 /* Mode register set cycle time (tMRD). */ 311 unsigned char tmrd_mclk; 312 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) 313 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 314 #endif 315 316 #ifdef CONFIG_SYS_FSL_DDR4 317 /* tXP=max(4nCK, 6ns) */ 318 int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ 319 unsigned int data_rate = get_ddr_freq(ctrl_num); 320 321 /* for faster clock, need more time for data setup */ 322 trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2; 323 324 /* 325 * for single quad-rank DIMM and two-slot DIMMs 326 * to avoid ODT overlap 327 */ 328 switch (avoid_odt_overlap(dimm_params)) { 329 case 2: 330 twrt_mclk = 2; 331 twwt_mclk = 2; 332 trrt_mclk = 2; 333 break; 334 default: 335 twrt_mclk = 1; 336 twwt_mclk = 1; 337 trrt_mclk = 0; 338 break; 339 } 340 341 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); 342 pre_pd_exit_mclk = act_pd_exit_mclk; 343 /* 344 * MRS_CYC = max(tMRD, tMOD) 345 * tMRD = 8nCK, tMOD = max(24nCK, 15ns) 346 */ 347 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000)); 348 #elif defined(CONFIG_SYS_FSL_DDR3) 349 unsigned int data_rate = get_ddr_freq(ctrl_num); 350 int txp; 351 unsigned int ip_rev; 352 int odt_overlap; 353 /* 354 * (tXARD and tXARDS). Empirical? 355 * The DDR3 spec has not tXARD, 356 * we use the tXP instead of it. 357 * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066 358 * max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133 359 * spec has not the tAXPD, we use 360 * tAXPD=1, need design to confirm. 361 */ 362 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000)); 363 364 ip_rev = fsl_ddr_get_version(ctrl_num); 365 if (ip_rev >= 0x40700) { 366 /* 367 * MRS_CYC = max(tMRD, tMOD) 368 * tMRD = 4nCK (8nCK for RDIMM) 369 * tMOD = max(12nCK, 15ns) 370 */ 371 tmrd_mclk = max((unsigned int)12, 372 picos_to_mclk(ctrl_num, 15000)); 373 } else { 374 /* 375 * MRS_CYC = tMRD 376 * tMRD = 4nCK (8nCK for RDIMM) 377 */ 378 if (popts->registered_dimm_en) 379 tmrd_mclk = 8; 380 else 381 tmrd_mclk = 4; 382 } 383 384 /* set the turnaround time */ 385 386 /* 387 * for single quad-rank DIMM and two-slot DIMMs 388 * to avoid ODT overlap 389 */ 390 odt_overlap = avoid_odt_overlap(dimm_params); 391 switch (odt_overlap) { 392 case 2: 393 twwt_mclk = 2; 394 trrt_mclk = 1; 395 break; 396 case 1: 397 twwt_mclk = 1; 398 trrt_mclk = 0; 399 break; 400 default: 401 break; 402 } 403 404 /* for faster clock, need more time for data setup */ 405 trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1; 406 407 if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving)) 408 twrt_mclk = 1; 409 410 if (popts->dynamic_power == 0) { /* powerdown is not used */ 411 act_pd_exit_mclk = 1; 412 pre_pd_exit_mclk = 1; 413 taxpd_mclk = 1; 414 } else { 415 /* act_pd_exit_mclk = tXARD, see above */ 416 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); 417 /* Mode register MR0[A12] is '1' - fast exit */ 418 pre_pd_exit_mclk = act_pd_exit_mclk; 419 taxpd_mclk = 1; 420 } 421 #else /* CONFIG_SYS_FSL_DDR2 */ 422 /* 423 * (tXARD and tXARDS). Empirical? 424 * tXARD = 2 for DDR2 425 * tXP=2 426 * tAXPD=8 427 */ 428 act_pd_exit_mclk = 2; 429 pre_pd_exit_mclk = 2; 430 taxpd_mclk = 8; 431 tmrd_mclk = 2; 432 #endif 433 434 if (popts->trwt_override) 435 trwt_mclk = popts->trwt; 436 437 ddr->timing_cfg_0 = (0 438 | ((trwt_mclk & 0x3) << 30) /* RWT */ 439 | ((twrt_mclk & 0x3) << 28) /* WRT */ 440 | ((trrt_mclk & 0x3) << 26) /* RRT */ 441 | ((twwt_mclk & 0x3) << 24) /* WWT */ 442 | ((act_pd_exit_mclk & 0xf) << 20) /* ACT_PD_EXIT */ 443 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */ 444 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */ 445 | ((tmrd_mclk & 0x1f) << 0) /* MRS_CYC */ 446 ); 447 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0); 448 } 449 #endif /* !defined(CONFIG_SYS_FSL_DDR1) */ 450 451 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ 452 static void set_timing_cfg_3(const unsigned int ctrl_num, 453 fsl_ddr_cfg_regs_t *ddr, 454 const memctl_options_t *popts, 455 const common_timing_params_t *common_dimm, 456 unsigned int cas_latency, 457 unsigned int additive_latency) 458 { 459 /* Extended precharge to activate interval (tRP) */ 460 unsigned int ext_pretoact = 0; 461 /* Extended Activate to precharge interval (tRAS) */ 462 unsigned int ext_acttopre = 0; 463 /* Extended activate to read/write interval (tRCD) */ 464 unsigned int ext_acttorw = 0; 465 /* Extended refresh recovery time (tRFC) */ 466 unsigned int ext_refrec; 467 /* Extended MCAS latency from READ cmd */ 468 unsigned int ext_caslat = 0; 469 /* Extended additive latency */ 470 unsigned int ext_add_lat = 0; 471 /* Extended last data to precharge interval (tWR) */ 472 unsigned int ext_wrrec = 0; 473 /* Control Adjust */ 474 unsigned int cntl_adj = 0; 475 476 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; 477 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; 478 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; 479 ext_caslat = (2 * cas_latency - 1) >> 4; 480 ext_add_lat = additive_latency >> 4; 481 #ifdef CONFIG_SYS_FSL_DDR4 482 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; 483 #else 484 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; 485 /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ 486 #endif 487 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + 488 (popts->otf_burst_chop_en ? 2 : 0)) >> 4; 489 490 ddr->timing_cfg_3 = (0 491 | ((ext_pretoact & 0x1) << 28) 492 | ((ext_acttopre & 0x3) << 24) 493 | ((ext_acttorw & 0x1) << 22) 494 | ((ext_refrec & 0x1F) << 16) 495 | ((ext_caslat & 0x3) << 12) 496 | ((ext_add_lat & 0x1) << 10) 497 | ((ext_wrrec & 0x1) << 8) 498 | ((cntl_adj & 0x7) << 0) 499 ); 500 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3); 501 } 502 503 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ 504 static void set_timing_cfg_1(const unsigned int ctrl_num, 505 fsl_ddr_cfg_regs_t *ddr, 506 const memctl_options_t *popts, 507 const common_timing_params_t *common_dimm, 508 unsigned int cas_latency) 509 { 510 /* Precharge-to-activate interval (tRP) */ 511 unsigned char pretoact_mclk; 512 /* Activate to precharge interval (tRAS) */ 513 unsigned char acttopre_mclk; 514 /* Activate to read/write interval (tRCD) */ 515 unsigned char acttorw_mclk; 516 /* CASLAT */ 517 unsigned char caslat_ctrl; 518 /* Refresh recovery time (tRFC) ; trfc_low */ 519 unsigned char refrec_ctrl; 520 /* Last data to precharge minimum interval (tWR) */ 521 unsigned char wrrec_mclk; 522 /* Activate-to-activate interval (tRRD) */ 523 unsigned char acttoact_mclk; 524 /* Last write data pair to read command issue interval (tWTR) */ 525 unsigned char wrtord_mclk; 526 #ifdef CONFIG_SYS_FSL_DDR4 527 /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */ 528 static const u8 wrrec_table[] = { 529 10, 10, 10, 10, 10, 530 10, 10, 10, 10, 10, 531 12, 12, 14, 14, 16, 532 16, 18, 18, 20, 20, 533 24, 24, 24, 24}; 534 #else 535 /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ 536 static const u8 wrrec_table[] = { 537 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; 538 #endif 539 540 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); 541 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); 542 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); 543 544 /* 545 * Translate CAS Latency to a DDR controller field value: 546 * 547 * CAS Lat DDR I DDR II Ctrl 548 * Clocks SPD Bit SPD Bit Value 549 * ------- ------- ------- ----- 550 * 1.0 0 0001 551 * 1.5 1 0010 552 * 2.0 2 2 0011 553 * 2.5 3 0100 554 * 3.0 4 3 0101 555 * 3.5 5 0110 556 * 4.0 4 0111 557 * 4.5 1000 558 * 5.0 5 1001 559 */ 560 #if defined(CONFIG_SYS_FSL_DDR1) 561 caslat_ctrl = (cas_latency + 1) & 0x07; 562 #elif defined(CONFIG_SYS_FSL_DDR2) 563 caslat_ctrl = 2 * cas_latency - 1; 564 #else 565 /* 566 * if the CAS latency more than 8 cycle, 567 * we need set extend bit for it at 568 * TIMING_CFG_3[EXT_CASLAT] 569 */ 570 if (fsl_ddr_get_version(ctrl_num) <= 0x40400) 571 caslat_ctrl = 2 * cas_latency - 1; 572 else 573 caslat_ctrl = (cas_latency - 1) << 1; 574 #endif 575 576 #ifdef CONFIG_SYS_FSL_DDR4 577 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; 578 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); 579 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); 580 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500)); 581 if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) 582 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); 583 else 584 wrrec_mclk = wrrec_table[wrrec_mclk - 1]; 585 #else 586 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; 587 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); 588 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); 589 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); 590 if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) 591 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); 592 else 593 wrrec_mclk = wrrec_table[wrrec_mclk - 1]; 594 #endif 595 if (popts->otf_burst_chop_en) 596 wrrec_mclk += 2; 597 598 /* 599 * JEDEC has min requirement for tRRD 600 */ 601 #if defined(CONFIG_SYS_FSL_DDR3) 602 if (acttoact_mclk < 4) 603 acttoact_mclk = 4; 604 #endif 605 /* 606 * JEDEC has some min requirements for tWTR 607 */ 608 #if defined(CONFIG_SYS_FSL_DDR2) 609 if (wrtord_mclk < 2) 610 wrtord_mclk = 2; 611 #elif defined(CONFIG_SYS_FSL_DDR3) 612 if (wrtord_mclk < 4) 613 wrtord_mclk = 4; 614 #endif 615 if (popts->otf_burst_chop_en) 616 wrtord_mclk += 2; 617 618 ddr->timing_cfg_1 = (0 619 | ((pretoact_mclk & 0x0F) << 28) 620 | ((acttopre_mclk & 0x0F) << 24) 621 | ((acttorw_mclk & 0xF) << 20) 622 | ((caslat_ctrl & 0xF) << 16) 623 | ((refrec_ctrl & 0xF) << 12) 624 | ((wrrec_mclk & 0x0F) << 8) 625 | ((acttoact_mclk & 0x0F) << 4) 626 | ((wrtord_mclk & 0x0F) << 0) 627 ); 628 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1); 629 } 630 631 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ 632 static void set_timing_cfg_2(const unsigned int ctrl_num, 633 fsl_ddr_cfg_regs_t *ddr, 634 const memctl_options_t *popts, 635 const common_timing_params_t *common_dimm, 636 unsigned int cas_latency, 637 unsigned int additive_latency) 638 { 639 /* Additive latency */ 640 unsigned char add_lat_mclk; 641 /* CAS-to-preamble override */ 642 unsigned short cpo; 643 /* Write latency */ 644 unsigned char wr_lat; 645 /* Read to precharge (tRTP) */ 646 unsigned char rd_to_pre; 647 /* Write command to write data strobe timing adjustment */ 648 unsigned char wr_data_delay; 649 /* Minimum CKE pulse width (tCKE) */ 650 unsigned char cke_pls; 651 /* Window for four activates (tFAW) */ 652 unsigned short four_act; 653 #ifdef CONFIG_SYS_FSL_DDR3 654 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 655 #endif 656 657 /* FIXME add check that this must be less than acttorw_mclk */ 658 add_lat_mclk = additive_latency; 659 cpo = popts->cpo_override; 660 661 #if defined(CONFIG_SYS_FSL_DDR1) 662 /* 663 * This is a lie. It should really be 1, but if it is 664 * set to 1, bits overlap into the old controller's 665 * otherwise unused ACSM field. If we leave it 0, then 666 * the HW will magically treat it as 1 for DDR 1. Oh Yea. 667 */ 668 wr_lat = 0; 669 #elif defined(CONFIG_SYS_FSL_DDR2) 670 wr_lat = cas_latency - 1; 671 #else 672 wr_lat = compute_cas_write_latency(ctrl_num); 673 #endif 674 675 #ifdef CONFIG_SYS_FSL_DDR4 676 rd_to_pre = picos_to_mclk(ctrl_num, 7500); 677 #else 678 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); 679 #endif 680 /* 681 * JEDEC has some min requirements for tRTP 682 */ 683 #if defined(CONFIG_SYS_FSL_DDR2) 684 if (rd_to_pre < 2) 685 rd_to_pre = 2; 686 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 687 if (rd_to_pre < 4) 688 rd_to_pre = 4; 689 #endif 690 if (popts->otf_burst_chop_en) 691 rd_to_pre += 2; /* according to UM */ 692 693 wr_data_delay = popts->write_data_delay; 694 #ifdef CONFIG_SYS_FSL_DDR4 695 cpo = 0; 696 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000)); 697 #elif defined(CONFIG_SYS_FSL_DDR3) 698 /* 699 * cke pulse = max(3nCK, 7.5ns) for DDR3-800 700 * max(3nCK, 5.625ns) for DDR3-1066, 1333 701 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 702 */ 703 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 : 704 (mclk_ps > 1245 ? 5625 : 5000))); 705 #else 706 cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; 707 #endif 708 four_act = picos_to_mclk(ctrl_num, 709 popts->tfaw_window_four_activates_ps); 710 711 ddr->timing_cfg_2 = (0 712 | ((add_lat_mclk & 0xf) << 28) 713 | ((cpo & 0x1f) << 23) 714 | ((wr_lat & 0xf) << 19) 715 | (((wr_lat & 0x10) >> 4) << 18) 716 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) 717 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) 718 | ((cke_pls & 0x7) << 6) 719 | ((four_act & 0x3f) << 0) 720 ); 721 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2); 722 } 723 724 /* DDR SDRAM Register Control Word */ 725 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr, 726 const memctl_options_t *popts, 727 const common_timing_params_t *common_dimm) 728 { 729 if (common_dimm->all_dimms_registered && 730 !common_dimm->all_dimms_unbuffered) { 731 if (popts->rcw_override) { 732 ddr->ddr_sdram_rcw_1 = popts->rcw_1; 733 ddr->ddr_sdram_rcw_2 = popts->rcw_2; 734 } else { 735 ddr->ddr_sdram_rcw_1 = 736 common_dimm->rcw[0] << 28 | \ 737 common_dimm->rcw[1] << 24 | \ 738 common_dimm->rcw[2] << 20 | \ 739 common_dimm->rcw[3] << 16 | \ 740 common_dimm->rcw[4] << 12 | \ 741 common_dimm->rcw[5] << 8 | \ 742 common_dimm->rcw[6] << 4 | \ 743 common_dimm->rcw[7]; 744 ddr->ddr_sdram_rcw_2 = 745 common_dimm->rcw[8] << 28 | \ 746 common_dimm->rcw[9] << 24 | \ 747 common_dimm->rcw[10] << 20 | \ 748 common_dimm->rcw[11] << 16 | \ 749 common_dimm->rcw[12] << 12 | \ 750 common_dimm->rcw[13] << 8 | \ 751 common_dimm->rcw[14] << 4 | \ 752 common_dimm->rcw[15]; 753 } 754 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1); 755 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2); 756 } 757 } 758 759 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */ 760 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, 761 const memctl_options_t *popts, 762 const common_timing_params_t *common_dimm) 763 { 764 unsigned int mem_en; /* DDR SDRAM interface logic enable */ 765 unsigned int sren; /* Self refresh enable (during sleep) */ 766 unsigned int ecc_en; /* ECC enable. */ 767 unsigned int rd_en; /* Registered DIMM enable */ 768 unsigned int sdram_type; /* Type of SDRAM */ 769 unsigned int dyn_pwr; /* Dynamic power management mode */ 770 unsigned int dbw; /* DRAM dta bus width */ 771 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */ 772 unsigned int ncap = 0; /* Non-concurrent auto-precharge */ 773 unsigned int threet_en; /* Enable 3T timing */ 774 unsigned int twot_en; /* Enable 2T timing */ 775 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */ 776 unsigned int x32_en = 0; /* x32 enable */ 777 unsigned int pchb8 = 0; /* precharge bit 8 enable */ 778 unsigned int hse; /* Global half strength override */ 779 unsigned int acc_ecc_en = 0; /* Accumulated ECC enable */ 780 unsigned int mem_halt = 0; /* memory controller halt */ 781 unsigned int bi = 0; /* Bypass initialization */ 782 783 mem_en = 1; 784 sren = popts->self_refresh_in_sleep; 785 if (common_dimm->all_dimms_ecc_capable) { 786 /* Allow setting of ECC only if all DIMMs are ECC. */ 787 ecc_en = popts->ecc_mode; 788 } else { 789 ecc_en = 0; 790 } 791 792 if (common_dimm->all_dimms_registered && 793 !common_dimm->all_dimms_unbuffered) { 794 rd_en = 1; 795 twot_en = 0; 796 } else { 797 rd_en = 0; 798 twot_en = popts->twot_en; 799 } 800 801 sdram_type = CONFIG_FSL_SDRAM_TYPE; 802 803 dyn_pwr = popts->dynamic_power; 804 dbw = popts->data_bus_width; 805 /* 8-beat burst enable DDR-III case 806 * we must clear it when use the on-the-fly mode, 807 * must set it when use the 32-bits bus mode. 808 */ 809 if ((sdram_type == SDRAM_TYPE_DDR3) || 810 (sdram_type == SDRAM_TYPE_DDR4)) { 811 if (popts->burst_length == DDR_BL8) 812 eight_be = 1; 813 if (popts->burst_length == DDR_OTF) 814 eight_be = 0; 815 if (dbw == 0x1) 816 eight_be = 1; 817 } 818 819 threet_en = popts->threet_en; 820 ba_intlv_ctl = popts->ba_intlv_ctl; 821 hse = popts->half_strength_driver_enable; 822 823 /* set when ddr bus width < 64 */ 824 acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0; 825 826 ddr->ddr_sdram_cfg = (0 827 | ((mem_en & 0x1) << 31) 828 | ((sren & 0x1) << 30) 829 | ((ecc_en & 0x1) << 29) 830 | ((rd_en & 0x1) << 28) 831 | ((sdram_type & 0x7) << 24) 832 | ((dyn_pwr & 0x1) << 21) 833 | ((dbw & 0x3) << 19) 834 | ((eight_be & 0x1) << 18) 835 | ((ncap & 0x1) << 17) 836 | ((threet_en & 0x1) << 16) 837 | ((twot_en & 0x1) << 15) 838 | ((ba_intlv_ctl & 0x7F) << 8) 839 | ((x32_en & 0x1) << 5) 840 | ((pchb8 & 0x1) << 4) 841 | ((hse & 0x1) << 3) 842 | ((acc_ecc_en & 0x1) << 2) 843 | ((mem_halt & 0x1) << 1) 844 | ((bi & 0x1) << 0) 845 ); 846 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg); 847 } 848 849 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ 850 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, 851 fsl_ddr_cfg_regs_t *ddr, 852 const memctl_options_t *popts, 853 const unsigned int unq_mrs_en) 854 { 855 unsigned int frc_sr = 0; /* Force self refresh */ 856 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */ 857 unsigned int odt_cfg = 0; /* ODT configuration */ 858 unsigned int num_pr; /* Number of posted refreshes */ 859 unsigned int slow = 0; /* DDR will be run less than 1250 */ 860 unsigned int x4_en = 0; /* x4 DRAM enable */ 861 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ 862 unsigned int ap_en; /* Address Parity Enable */ 863 unsigned int d_init; /* DRAM data initialization */ 864 unsigned int rcw_en = 0; /* Register Control Word Enable */ 865 unsigned int md_en = 0; /* Mirrored DIMM Enable */ 866 unsigned int qd_en = 0; /* quad-rank DIMM Enable */ 867 int i; 868 #ifndef CONFIG_SYS_FSL_DDR4 869 unsigned int dll_rst_dis = 1; /* DLL reset disable */ 870 unsigned int dqs_cfg; /* DQS configuration */ 871 872 dqs_cfg = popts->dqs_config; 873 #endif 874 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 875 if (popts->cs_local_opts[i].odt_rd_cfg 876 || popts->cs_local_opts[i].odt_wr_cfg) { 877 odt_cfg = SDRAM_CFG2_ODT_ONLY_READ; 878 break; 879 } 880 } 881 sr_ie = popts->self_refresh_interrupt_en; 882 num_pr = 1; /* Make this configurable */ 883 884 /* 885 * 8572 manual says 886 * {TIMING_CFG_1[PRETOACT] 887 * + [DDR_SDRAM_CFG_2[NUM_PR] 888 * * ({EXT_REFREC || REFREC} + 8 + 2)]} 889 * << DDR_SDRAM_INTERVAL[REFINT] 890 */ 891 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 892 obc_cfg = popts->otf_burst_chop_en; 893 #else 894 obc_cfg = 0; 895 #endif 896 897 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) 898 slow = get_ddr_freq(ctrl_num) < 1249000000; 899 #endif 900 901 if (popts->registered_dimm_en) 902 rcw_en = 1; 903 904 /* DDR4 can have address parity for UDIMM and discrete */ 905 if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) && 906 (!popts->registered_dimm_en)) { 907 ap_en = 0; 908 } else { 909 ap_en = popts->ap_en; 910 } 911 912 x4_en = popts->x4_en ? 1 : 0; 913 914 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 915 /* Use the DDR controller to auto initialize memory. */ 916 d_init = popts->ecc_init_using_memctl; 917 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE; 918 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init); 919 #else 920 /* Memory will be initialized via DMA, or not at all. */ 921 d_init = 0; 922 #endif 923 924 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 925 md_en = popts->mirrored_dimm; 926 #endif 927 qd_en = popts->quad_rank_present ? 1 : 0; 928 ddr->ddr_sdram_cfg_2 = (0 929 | ((frc_sr & 0x1) << 31) 930 | ((sr_ie & 0x1) << 30) 931 #ifndef CONFIG_SYS_FSL_DDR4 932 | ((dll_rst_dis & 0x1) << 29) 933 | ((dqs_cfg & 0x3) << 26) 934 #endif 935 | ((odt_cfg & 0x3) << 21) 936 | ((num_pr & 0xf) << 12) 937 | ((slow & 1) << 11) 938 | (x4_en << 10) 939 | (qd_en << 9) 940 | (unq_mrs_en << 8) 941 | ((obc_cfg & 0x1) << 6) 942 | ((ap_en & 0x1) << 5) 943 | ((d_init & 0x1) << 4) 944 | ((rcw_en & 0x1) << 2) 945 | ((md_en & 0x1) << 0) 946 ); 947 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2); 948 } 949 950 #ifdef CONFIG_SYS_FSL_DDR4 951 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ 952 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, 953 fsl_ddr_cfg_regs_t *ddr, 954 const memctl_options_t *popts, 955 const common_timing_params_t *common_dimm, 956 const unsigned int unq_mrs_en) 957 { 958 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ 959 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ 960 int i; 961 unsigned int wr_crc = 0; /* Disable */ 962 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ 963 unsigned int srt = 0; /* self-refresh temerature, normal range */ 964 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; 965 unsigned int mpr = 0; /* serial */ 966 unsigned int wc_lat; 967 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 968 969 if (popts->rtt_override) 970 rtt_wr = popts->rtt_wr_override_value; 971 else 972 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; 973 974 if (common_dimm->extended_op_srt) 975 srt = common_dimm->extended_op_srt; 976 977 esdmode2 = (0 978 | ((wr_crc & 0x1) << 12) 979 | ((rtt_wr & 0x3) << 9) 980 | ((srt & 0x3) << 6) 981 | ((cwl & 0x7) << 3)); 982 983 if (mclk_ps >= 1250) 984 wc_lat = 0; 985 else if (mclk_ps >= 833) 986 wc_lat = 1; 987 else 988 wc_lat = 2; 989 990 esdmode3 = (0 991 | ((mpr & 0x3) << 11) 992 | ((wc_lat & 0x3) << 9)); 993 994 ddr->ddr_sdram_mode_2 = (0 995 | ((esdmode2 & 0xFFFF) << 16) 996 | ((esdmode3 & 0xFFFF) << 0) 997 ); 998 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); 999 1000 if (unq_mrs_en) { /* unique mode registers are supported */ 1001 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1002 if (popts->rtt_override) 1003 rtt_wr = popts->rtt_wr_override_value; 1004 else 1005 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; 1006 1007 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ 1008 esdmode2 |= (rtt_wr & 0x3) << 9; 1009 switch (i) { 1010 case 1: 1011 ddr->ddr_sdram_mode_4 = (0 1012 | ((esdmode2 & 0xFFFF) << 16) 1013 | ((esdmode3 & 0xFFFF) << 0) 1014 ); 1015 break; 1016 case 2: 1017 ddr->ddr_sdram_mode_6 = (0 1018 | ((esdmode2 & 0xFFFF) << 16) 1019 | ((esdmode3 & 0xFFFF) << 0) 1020 ); 1021 break; 1022 case 3: 1023 ddr->ddr_sdram_mode_8 = (0 1024 | ((esdmode2 & 0xFFFF) << 16) 1025 | ((esdmode3 & 0xFFFF) << 0) 1026 ); 1027 break; 1028 } 1029 } 1030 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", 1031 ddr->ddr_sdram_mode_4); 1032 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", 1033 ddr->ddr_sdram_mode_6); 1034 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", 1035 ddr->ddr_sdram_mode_8); 1036 } 1037 } 1038 #elif defined(CONFIG_SYS_FSL_DDR3) 1039 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ 1040 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, 1041 fsl_ddr_cfg_regs_t *ddr, 1042 const memctl_options_t *popts, 1043 const common_timing_params_t *common_dimm, 1044 const unsigned int unq_mrs_en) 1045 { 1046 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ 1047 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ 1048 int i; 1049 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ 1050 unsigned int srt = 0; /* self-refresh temerature, normal range */ 1051 unsigned int asr = 0; /* auto self-refresh disable */ 1052 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; 1053 unsigned int pasr = 0; /* partial array self refresh disable */ 1054 1055 if (popts->rtt_override) 1056 rtt_wr = popts->rtt_wr_override_value; 1057 else 1058 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr; 1059 1060 if (common_dimm->extended_op_srt) 1061 srt = common_dimm->extended_op_srt; 1062 1063 esdmode2 = (0 1064 | ((rtt_wr & 0x3) << 9) 1065 | ((srt & 0x1) << 7) 1066 | ((asr & 0x1) << 6) 1067 | ((cwl & 0x7) << 3) 1068 | ((pasr & 0x7) << 0)); 1069 ddr->ddr_sdram_mode_2 = (0 1070 | ((esdmode2 & 0xFFFF) << 16) 1071 | ((esdmode3 & 0xFFFF) << 0) 1072 ); 1073 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); 1074 1075 if (unq_mrs_en) { /* unique mode registers are supported */ 1076 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1077 if (popts->rtt_override) 1078 rtt_wr = popts->rtt_wr_override_value; 1079 else 1080 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr; 1081 1082 esdmode2 &= 0xF9FF; /* clear bit 10, 9 */ 1083 esdmode2 |= (rtt_wr & 0x3) << 9; 1084 switch (i) { 1085 case 1: 1086 ddr->ddr_sdram_mode_4 = (0 1087 | ((esdmode2 & 0xFFFF) << 16) 1088 | ((esdmode3 & 0xFFFF) << 0) 1089 ); 1090 break; 1091 case 2: 1092 ddr->ddr_sdram_mode_6 = (0 1093 | ((esdmode2 & 0xFFFF) << 16) 1094 | ((esdmode3 & 0xFFFF) << 0) 1095 ); 1096 break; 1097 case 3: 1098 ddr->ddr_sdram_mode_8 = (0 1099 | ((esdmode2 & 0xFFFF) << 16) 1100 | ((esdmode3 & 0xFFFF) << 0) 1101 ); 1102 break; 1103 } 1104 } 1105 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n", 1106 ddr->ddr_sdram_mode_4); 1107 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n", 1108 ddr->ddr_sdram_mode_6); 1109 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n", 1110 ddr->ddr_sdram_mode_8); 1111 } 1112 } 1113 1114 #else /* for DDR2 and DDR1 */ 1115 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ 1116 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, 1117 fsl_ddr_cfg_regs_t *ddr, 1118 const memctl_options_t *popts, 1119 const common_timing_params_t *common_dimm, 1120 const unsigned int unq_mrs_en) 1121 { 1122 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ 1123 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ 1124 1125 ddr->ddr_sdram_mode_2 = (0 1126 | ((esdmode2 & 0xFFFF) << 16) 1127 | ((esdmode3 & 0xFFFF) << 0) 1128 ); 1129 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2); 1130 } 1131 #endif 1132 1133 #ifdef CONFIG_SYS_FSL_DDR4 1134 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */ 1135 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, 1136 const memctl_options_t *popts, 1137 const common_timing_params_t *common_dimm, 1138 const unsigned int unq_mrs_en) 1139 { 1140 int i; 1141 unsigned short esdmode4 = 0; /* Extended SDRAM mode 4 */ 1142 unsigned short esdmode5; /* Extended SDRAM mode 5 */ 1143 int rtt_park = 0; 1144 bool four_cs = false; 1145 const unsigned int mclk_ps = get_memory_clk_period_ps(0); 1146 1147 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4 1148 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && 1149 (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) && 1150 (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) && 1151 (ddr->cs[3].config & SDRAM_CS_CONFIG_EN)) 1152 four_cs = true; 1153 #endif 1154 if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) { 1155 esdmode5 = 0x00000500; /* Data mask enable, RTT_PARK CS0 */ 1156 rtt_park = four_cs ? 0 : 1; 1157 } else { 1158 esdmode5 = 0x00000400; /* Data mask enabled */ 1159 } 1160 1161 /* set command/address parity latency */ 1162 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 1163 if (mclk_ps >= 935) { 1164 /* for DDR4-1600/1866/2133 */ 1165 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; 1166 } else if (mclk_ps >= 833) { 1167 /* for DDR4-2400 */ 1168 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; 1169 } else { 1170 printf("parity: mclk_ps = %d not supported\n", mclk_ps); 1171 } 1172 } 1173 1174 ddr->ddr_sdram_mode_9 = (0 1175 | ((esdmode4 & 0xffff) << 16) 1176 | ((esdmode5 & 0xffff) << 0) 1177 ); 1178 1179 /* Normally only the first enabled CS use 0x500, others use 0x400 1180 * But when four chip-selects are all enabled, all mode registers 1181 * need 0x500 to park. 1182 */ 1183 1184 debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9); 1185 if (unq_mrs_en) { /* unique mode registers are supported */ 1186 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1187 if (!rtt_park && 1188 (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) { 1189 esdmode5 |= 0x00000500; /* RTT_PARK */ 1190 rtt_park = four_cs ? 0 : 1; 1191 } else { 1192 esdmode5 = 0x00000400; 1193 } 1194 1195 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 1196 if (mclk_ps >= 935) { 1197 /* for DDR4-1600/1866/2133 */ 1198 esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; 1199 } else if (mclk_ps >= 833) { 1200 /* for DDR4-2400 */ 1201 esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; 1202 } else { 1203 printf("parity: mclk_ps = %d not supported\n", 1204 mclk_ps); 1205 } 1206 } 1207 1208 switch (i) { 1209 case 1: 1210 ddr->ddr_sdram_mode_11 = (0 1211 | ((esdmode4 & 0xFFFF) << 16) 1212 | ((esdmode5 & 0xFFFF) << 0) 1213 ); 1214 break; 1215 case 2: 1216 ddr->ddr_sdram_mode_13 = (0 1217 | ((esdmode4 & 0xFFFF) << 16) 1218 | ((esdmode5 & 0xFFFF) << 0) 1219 ); 1220 break; 1221 case 3: 1222 ddr->ddr_sdram_mode_15 = (0 1223 | ((esdmode4 & 0xFFFF) << 16) 1224 | ((esdmode5 & 0xFFFF) << 0) 1225 ); 1226 break; 1227 } 1228 } 1229 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n", 1230 ddr->ddr_sdram_mode_11); 1231 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n", 1232 ddr->ddr_sdram_mode_13); 1233 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n", 1234 ddr->ddr_sdram_mode_15); 1235 } 1236 } 1237 1238 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ 1239 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, 1240 fsl_ddr_cfg_regs_t *ddr, 1241 const memctl_options_t *popts, 1242 const common_timing_params_t *common_dimm, 1243 const unsigned int unq_mrs_en) 1244 { 1245 int i; 1246 unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ 1247 unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ 1248 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); 1249 1250 esdmode6 = ((tccdl_min - 4) & 0x7) << 10; 1251 1252 if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) 1253 esdmode6 |= 1 << 6; /* Range 2 */ 1254 1255 ddr->ddr_sdram_mode_10 = (0 1256 | ((esdmode6 & 0xffff) << 16) 1257 | ((esdmode7 & 0xffff) << 0) 1258 ); 1259 debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10); 1260 if (unq_mrs_en) { /* unique mode registers are supported */ 1261 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1262 switch (i) { 1263 case 1: 1264 ddr->ddr_sdram_mode_12 = (0 1265 | ((esdmode6 & 0xFFFF) << 16) 1266 | ((esdmode7 & 0xFFFF) << 0) 1267 ); 1268 break; 1269 case 2: 1270 ddr->ddr_sdram_mode_14 = (0 1271 | ((esdmode6 & 0xFFFF) << 16) 1272 | ((esdmode7 & 0xFFFF) << 0) 1273 ); 1274 break; 1275 case 3: 1276 ddr->ddr_sdram_mode_16 = (0 1277 | ((esdmode6 & 0xFFFF) << 16) 1278 | ((esdmode7 & 0xFFFF) << 0) 1279 ); 1280 break; 1281 } 1282 } 1283 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n", 1284 ddr->ddr_sdram_mode_12); 1285 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n", 1286 ddr->ddr_sdram_mode_14); 1287 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n", 1288 ddr->ddr_sdram_mode_16); 1289 } 1290 } 1291 1292 #endif 1293 1294 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ 1295 static void set_ddr_sdram_interval(const unsigned int ctrl_num, 1296 fsl_ddr_cfg_regs_t *ddr, 1297 const memctl_options_t *popts, 1298 const common_timing_params_t *common_dimm) 1299 { 1300 unsigned int refint; /* Refresh interval */ 1301 unsigned int bstopre; /* Precharge interval */ 1302 1303 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); 1304 1305 bstopre = popts->bstopre; 1306 1307 /* refint field used 0x3FFF in earlier controllers */ 1308 ddr->ddr_sdram_interval = (0 1309 | ((refint & 0xFFFF) << 16) 1310 | ((bstopre & 0x3FFF) << 0) 1311 ); 1312 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval); 1313 } 1314 1315 #ifdef CONFIG_SYS_FSL_DDR4 1316 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ 1317 static void set_ddr_sdram_mode(const unsigned int ctrl_num, 1318 fsl_ddr_cfg_regs_t *ddr, 1319 const memctl_options_t *popts, 1320 const common_timing_params_t *common_dimm, 1321 unsigned int cas_latency, 1322 unsigned int additive_latency, 1323 const unsigned int unq_mrs_en) 1324 { 1325 int i; 1326 unsigned short esdmode; /* Extended SDRAM mode */ 1327 unsigned short sdmode; /* SDRAM mode */ 1328 1329 /* Mode Register - MR1 */ 1330 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ 1331 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ 1332 unsigned int rtt; 1333 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ 1334 unsigned int al = 0; /* Posted CAS# additive latency (AL) */ 1335 unsigned int dic = 0; /* Output driver impedance, 40ohm */ 1336 unsigned int dll_en = 1; /* DLL Enable 1=Enable (Normal), 1337 0=Disable (Test/Debug) */ 1338 1339 /* Mode Register - MR0 */ 1340 unsigned int wr = 0; /* Write Recovery */ 1341 unsigned int dll_rst; /* DLL Reset */ 1342 unsigned int mode; /* Normal=0 or Test=1 */ 1343 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ 1344 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ 1345 unsigned int bt; 1346 unsigned int bl; /* BL: Burst Length */ 1347 1348 unsigned int wr_mclk; 1349 /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */ 1350 static const u8 wr_table[] = { 1351 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6}; 1352 /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */ 1353 static const u8 cas_latency_table[] = { 1354 0, 1, 2, 3, 4, 5, 6, 7, 8, 8, 1355 9, 9, 10, 10, 11, 11}; 1356 1357 if (popts->rtt_override) 1358 rtt = popts->rtt_override_value; 1359 else 1360 rtt = popts->cs_local_opts[0].odt_rtt_norm; 1361 1362 if (additive_latency == (cas_latency - 1)) 1363 al = 1; 1364 if (additive_latency == (cas_latency - 2)) 1365 al = 2; 1366 1367 if (popts->quad_rank_present) 1368 dic = 1; /* output driver impedance 240/7 ohm */ 1369 1370 /* 1371 * The esdmode value will also be used for writing 1372 * MR1 during write leveling for DDR3, although the 1373 * bits specifically related to the write leveling 1374 * scheme will be handled automatically by the DDR 1375 * controller. so we set the wrlvl_en = 0 here. 1376 */ 1377 esdmode = (0 1378 | ((qoff & 0x1) << 12) 1379 | ((tdqs_en & 0x1) << 11) 1380 | ((rtt & 0x7) << 8) 1381 | ((wrlvl_en & 0x1) << 7) 1382 | ((al & 0x3) << 3) 1383 | ((dic & 0x3) << 1) /* DIC field is split */ 1384 | ((dll_en & 0x1) << 0) 1385 ); 1386 1387 /* 1388 * DLL control for precharge PD 1389 * 0=slow exit DLL off (tXPDLL) 1390 * 1=fast exit DLL on (tXP) 1391 */ 1392 1393 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); 1394 if (wr_mclk <= 24) { 1395 wr = wr_table[wr_mclk - 10]; 1396 } else { 1397 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n", 1398 wr_mclk); 1399 } 1400 1401 dll_rst = 0; /* dll no reset */ 1402 mode = 0; /* normal mode */ 1403 1404 /* look up table to get the cas latency bits */ 1405 if (cas_latency >= 9 && cas_latency <= 24) 1406 caslat = cas_latency_table[cas_latency - 9]; 1407 else 1408 printf("Error: unsupported cas latency for mode register\n"); 1409 1410 bt = 0; /* Nibble sequential */ 1411 1412 switch (popts->burst_length) { 1413 case DDR_BL8: 1414 bl = 0; 1415 break; 1416 case DDR_OTF: 1417 bl = 1; 1418 break; 1419 case DDR_BC4: 1420 bl = 2; 1421 break; 1422 default: 1423 printf("Error: invalid burst length of %u specified. ", 1424 popts->burst_length); 1425 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n"); 1426 bl = 1; 1427 break; 1428 } 1429 1430 sdmode = (0 1431 | ((wr & 0x7) << 9) 1432 | ((dll_rst & 0x1) << 8) 1433 | ((mode & 0x1) << 7) 1434 | (((caslat >> 1) & 0x7) << 4) 1435 | ((bt & 0x1) << 3) 1436 | ((caslat & 1) << 2) 1437 | ((bl & 0x3) << 0) 1438 ); 1439 1440 ddr->ddr_sdram_mode = (0 1441 | ((esdmode & 0xFFFF) << 16) 1442 | ((sdmode & 0xFFFF) << 0) 1443 ); 1444 1445 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); 1446 1447 if (unq_mrs_en) { /* unique mode registers are supported */ 1448 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1449 if (popts->rtt_override) 1450 rtt = popts->rtt_override_value; 1451 else 1452 rtt = popts->cs_local_opts[i].odt_rtt_norm; 1453 1454 esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */ 1455 esdmode |= (rtt & 0x7) << 8; 1456 switch (i) { 1457 case 1: 1458 ddr->ddr_sdram_mode_3 = (0 1459 | ((esdmode & 0xFFFF) << 16) 1460 | ((sdmode & 0xFFFF) << 0) 1461 ); 1462 break; 1463 case 2: 1464 ddr->ddr_sdram_mode_5 = (0 1465 | ((esdmode & 0xFFFF) << 16) 1466 | ((sdmode & 0xFFFF) << 0) 1467 ); 1468 break; 1469 case 3: 1470 ddr->ddr_sdram_mode_7 = (0 1471 | ((esdmode & 0xFFFF) << 16) 1472 | ((sdmode & 0xFFFF) << 0) 1473 ); 1474 break; 1475 } 1476 } 1477 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", 1478 ddr->ddr_sdram_mode_3); 1479 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1480 ddr->ddr_sdram_mode_5); 1481 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1482 ddr->ddr_sdram_mode_5); 1483 } 1484 } 1485 1486 #elif defined(CONFIG_SYS_FSL_DDR3) 1487 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ 1488 static void set_ddr_sdram_mode(const unsigned int ctrl_num, 1489 fsl_ddr_cfg_regs_t *ddr, 1490 const memctl_options_t *popts, 1491 const common_timing_params_t *common_dimm, 1492 unsigned int cas_latency, 1493 unsigned int additive_latency, 1494 const unsigned int unq_mrs_en) 1495 { 1496 int i; 1497 unsigned short esdmode; /* Extended SDRAM mode */ 1498 unsigned short sdmode; /* SDRAM mode */ 1499 1500 /* Mode Register - MR1 */ 1501 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */ 1502 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */ 1503 unsigned int rtt; 1504 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */ 1505 unsigned int al = 0; /* Posted CAS# additive latency (AL) */ 1506 unsigned int dic = 0; /* Output driver impedance, 40ohm */ 1507 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), 1508 1=Disable (Test/Debug) */ 1509 1510 /* Mode Register - MR0 */ 1511 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */ 1512 unsigned int wr = 0; /* Write Recovery */ 1513 unsigned int dll_rst; /* DLL Reset */ 1514 unsigned int mode; /* Normal=0 or Test=1 */ 1515 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */ 1516 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */ 1517 unsigned int bt; 1518 unsigned int bl; /* BL: Burst Length */ 1519 1520 unsigned int wr_mclk; 1521 /* 1522 * DDR_SDRAM_MODE doesn't support 9,11,13,15 1523 * Please refer JEDEC Standard No. 79-3E for Mode Register MR0 1524 * for this table 1525 */ 1526 static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0}; 1527 1528 if (popts->rtt_override) 1529 rtt = popts->rtt_override_value; 1530 else 1531 rtt = popts->cs_local_opts[0].odt_rtt_norm; 1532 1533 if (additive_latency == (cas_latency - 1)) 1534 al = 1; 1535 if (additive_latency == (cas_latency - 2)) 1536 al = 2; 1537 1538 if (popts->quad_rank_present) 1539 dic = 1; /* output driver impedance 240/7 ohm */ 1540 1541 /* 1542 * The esdmode value will also be used for writing 1543 * MR1 during write leveling for DDR3, although the 1544 * bits specifically related to the write leveling 1545 * scheme will be handled automatically by the DDR 1546 * controller. so we set the wrlvl_en = 0 here. 1547 */ 1548 esdmode = (0 1549 | ((qoff & 0x1) << 12) 1550 | ((tdqs_en & 0x1) << 11) 1551 | ((rtt & 0x4) << 7) /* rtt field is split */ 1552 | ((wrlvl_en & 0x1) << 7) 1553 | ((rtt & 0x2) << 5) /* rtt field is split */ 1554 | ((dic & 0x2) << 4) /* DIC field is split */ 1555 | ((al & 0x3) << 3) 1556 | ((rtt & 0x1) << 2) /* rtt field is split */ 1557 | ((dic & 0x1) << 1) /* DIC field is split */ 1558 | ((dll_en & 0x1) << 0) 1559 ); 1560 1561 /* 1562 * DLL control for precharge PD 1563 * 0=slow exit DLL off (tXPDLL) 1564 * 1=fast exit DLL on (tXP) 1565 */ 1566 dll_on = 1; 1567 1568 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); 1569 if (wr_mclk <= 16) { 1570 wr = wr_table[wr_mclk - 5]; 1571 } else { 1572 printf("Error: unsupported write recovery for mode register " 1573 "wr_mclk = %d\n", wr_mclk); 1574 } 1575 1576 dll_rst = 0; /* dll no reset */ 1577 mode = 0; /* normal mode */ 1578 1579 /* look up table to get the cas latency bits */ 1580 if (cas_latency >= 5 && cas_latency <= 16) { 1581 unsigned char cas_latency_table[] = { 1582 0x2, /* 5 clocks */ 1583 0x4, /* 6 clocks */ 1584 0x6, /* 7 clocks */ 1585 0x8, /* 8 clocks */ 1586 0xa, /* 9 clocks */ 1587 0xc, /* 10 clocks */ 1588 0xe, /* 11 clocks */ 1589 0x1, /* 12 clocks */ 1590 0x3, /* 13 clocks */ 1591 0x5, /* 14 clocks */ 1592 0x7, /* 15 clocks */ 1593 0x9, /* 16 clocks */ 1594 }; 1595 caslat = cas_latency_table[cas_latency - 5]; 1596 } else { 1597 printf("Error: unsupported cas latency for mode register\n"); 1598 } 1599 1600 bt = 0; /* Nibble sequential */ 1601 1602 switch (popts->burst_length) { 1603 case DDR_BL8: 1604 bl = 0; 1605 break; 1606 case DDR_OTF: 1607 bl = 1; 1608 break; 1609 case DDR_BC4: 1610 bl = 2; 1611 break; 1612 default: 1613 printf("Error: invalid burst length of %u specified. " 1614 " Defaulting to on-the-fly BC4 or BL8 beats.\n", 1615 popts->burst_length); 1616 bl = 1; 1617 break; 1618 } 1619 1620 sdmode = (0 1621 | ((dll_on & 0x1) << 12) 1622 | ((wr & 0x7) << 9) 1623 | ((dll_rst & 0x1) << 8) 1624 | ((mode & 0x1) << 7) 1625 | (((caslat >> 1) & 0x7) << 4) 1626 | ((bt & 0x1) << 3) 1627 | ((caslat & 1) << 2) 1628 | ((bl & 0x3) << 0) 1629 ); 1630 1631 ddr->ddr_sdram_mode = (0 1632 | ((esdmode & 0xFFFF) << 16) 1633 | ((sdmode & 0xFFFF) << 0) 1634 ); 1635 1636 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); 1637 1638 if (unq_mrs_en) { /* unique mode registers are supported */ 1639 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 1640 if (popts->rtt_override) 1641 rtt = popts->rtt_override_value; 1642 else 1643 rtt = popts->cs_local_opts[i].odt_rtt_norm; 1644 1645 esdmode &= 0xFDBB; /* clear bit 9,6,2 */ 1646 esdmode |= (0 1647 | ((rtt & 0x4) << 7) /* rtt field is split */ 1648 | ((rtt & 0x2) << 5) /* rtt field is split */ 1649 | ((rtt & 0x1) << 2) /* rtt field is split */ 1650 ); 1651 switch (i) { 1652 case 1: 1653 ddr->ddr_sdram_mode_3 = (0 1654 | ((esdmode & 0xFFFF) << 16) 1655 | ((sdmode & 0xFFFF) << 0) 1656 ); 1657 break; 1658 case 2: 1659 ddr->ddr_sdram_mode_5 = (0 1660 | ((esdmode & 0xFFFF) << 16) 1661 | ((sdmode & 0xFFFF) << 0) 1662 ); 1663 break; 1664 case 3: 1665 ddr->ddr_sdram_mode_7 = (0 1666 | ((esdmode & 0xFFFF) << 16) 1667 | ((sdmode & 0xFFFF) << 0) 1668 ); 1669 break; 1670 } 1671 } 1672 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n", 1673 ddr->ddr_sdram_mode_3); 1674 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1675 ddr->ddr_sdram_mode_5); 1676 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n", 1677 ddr->ddr_sdram_mode_5); 1678 } 1679 } 1680 1681 #else /* !CONFIG_SYS_FSL_DDR3 */ 1682 1683 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ 1684 static void set_ddr_sdram_mode(const unsigned int ctrl_num, 1685 fsl_ddr_cfg_regs_t *ddr, 1686 const memctl_options_t *popts, 1687 const common_timing_params_t *common_dimm, 1688 unsigned int cas_latency, 1689 unsigned int additive_latency, 1690 const unsigned int unq_mrs_en) 1691 { 1692 unsigned short esdmode; /* Extended SDRAM mode */ 1693 unsigned short sdmode; /* SDRAM mode */ 1694 1695 /* 1696 * FIXME: This ought to be pre-calculated in a 1697 * technology-specific routine, 1698 * e.g. compute_DDR2_mode_register(), and then the 1699 * sdmode and esdmode passed in as part of common_dimm. 1700 */ 1701 1702 /* Extended Mode Register */ 1703 unsigned int mrs = 0; /* Mode Register Set */ 1704 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */ 1705 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */ 1706 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */ 1707 unsigned int ocd = 0; /* 0x0=OCD not supported, 1708 0x7=OCD default state */ 1709 unsigned int rtt; 1710 unsigned int al; /* Posted CAS# additive latency (AL) */ 1711 unsigned int ods = 0; /* Output Drive Strength: 1712 0 = Full strength (18ohm) 1713 1 = Reduced strength (4ohm) */ 1714 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal), 1715 1=Disable (Test/Debug) */ 1716 1717 /* Mode Register (MR) */ 1718 unsigned int mr; /* Mode Register Definition */ 1719 unsigned int pd; /* Power-Down Mode */ 1720 unsigned int wr; /* Write Recovery */ 1721 unsigned int dll_res; /* DLL Reset */ 1722 unsigned int mode; /* Normal=0 or Test=1 */ 1723 unsigned int caslat = 0;/* CAS# latency */ 1724 /* BT: Burst Type (0=Sequential, 1=Interleaved) */ 1725 unsigned int bt; 1726 unsigned int bl; /* BL: Burst Length */ 1727 1728 dqs_en = !popts->dqs_config; 1729 rtt = fsl_ddr_get_rtt(); 1730 1731 al = additive_latency; 1732 1733 esdmode = (0 1734 | ((mrs & 0x3) << 14) 1735 | ((outputs & 0x1) << 12) 1736 | ((rdqs_en & 0x1) << 11) 1737 | ((dqs_en & 0x1) << 10) 1738 | ((ocd & 0x7) << 7) 1739 | ((rtt & 0x2) << 5) /* rtt field is split */ 1740 | ((al & 0x7) << 3) 1741 | ((rtt & 0x1) << 2) /* rtt field is split */ 1742 | ((ods & 0x1) << 1) 1743 | ((dll_en & 0x1) << 0) 1744 ); 1745 1746 mr = 0; /* FIXME: CHECKME */ 1747 1748 /* 1749 * 0 = Fast Exit (Normal) 1750 * 1 = Slow Exit (Low Power) 1751 */ 1752 pd = 0; 1753 1754 #if defined(CONFIG_SYS_FSL_DDR1) 1755 wr = 0; /* Historical */ 1756 #elif defined(CONFIG_SYS_FSL_DDR2) 1757 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); 1758 #endif 1759 dll_res = 0; 1760 mode = 0; 1761 1762 #if defined(CONFIG_SYS_FSL_DDR1) 1763 if (1 <= cas_latency && cas_latency <= 4) { 1764 unsigned char mode_caslat_table[4] = { 1765 0x5, /* 1.5 clocks */ 1766 0x2, /* 2.0 clocks */ 1767 0x6, /* 2.5 clocks */ 1768 0x3 /* 3.0 clocks */ 1769 }; 1770 caslat = mode_caslat_table[cas_latency - 1]; 1771 } else { 1772 printf("Warning: unknown cas_latency %d\n", cas_latency); 1773 } 1774 #elif defined(CONFIG_SYS_FSL_DDR2) 1775 caslat = cas_latency; 1776 #endif 1777 bt = 0; 1778 1779 switch (popts->burst_length) { 1780 case DDR_BL4: 1781 bl = 2; 1782 break; 1783 case DDR_BL8: 1784 bl = 3; 1785 break; 1786 default: 1787 printf("Error: invalid burst length of %u specified. " 1788 " Defaulting to 4 beats.\n", 1789 popts->burst_length); 1790 bl = 2; 1791 break; 1792 } 1793 1794 sdmode = (0 1795 | ((mr & 0x3) << 14) 1796 | ((pd & 0x1) << 12) 1797 | ((wr & 0x7) << 9) 1798 | ((dll_res & 0x1) << 8) 1799 | ((mode & 0x1) << 7) 1800 | ((caslat & 0x7) << 4) 1801 | ((bt & 0x1) << 3) 1802 | ((bl & 0x7) << 0) 1803 ); 1804 1805 ddr->ddr_sdram_mode = (0 1806 | ((esdmode & 0xFFFF) << 16) 1807 | ((sdmode & 0xFFFF) << 0) 1808 ); 1809 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode); 1810 } 1811 #endif 1812 1813 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */ 1814 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr) 1815 { 1816 unsigned int init_value; /* Initialization value */ 1817 1818 #ifdef CONFIG_MEM_INIT_VALUE 1819 init_value = CONFIG_MEM_INIT_VALUE; 1820 #else 1821 init_value = 0xDEADBEEF; 1822 #endif 1823 ddr->ddr_data_init = init_value; 1824 } 1825 1826 /* 1827 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL) 1828 * The old controller on the 8540/60 doesn't have this register. 1829 * Hope it's OK to set it (to 0) anyway. 1830 */ 1831 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, 1832 const memctl_options_t *popts) 1833 { 1834 unsigned int clk_adjust; /* Clock adjust */ 1835 unsigned int ss_en = 0; /* Source synchronous enable */ 1836 1837 #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555) 1838 /* Per FSL Application Note: AN2805 */ 1839 ss_en = 1; 1840 #endif 1841 if (fsl_ddr_get_version(0) >= 0x40701) { 1842 /* clk_adjust in 5-bits on T-series and LS-series */ 1843 clk_adjust = (popts->clk_adjust & 0x1F) << 22; 1844 } else { 1845 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */ 1846 clk_adjust = (popts->clk_adjust & 0xF) << 23; 1847 } 1848 1849 ddr->ddr_sdram_clk_cntl = (0 1850 | ((ss_en & 0x1) << 31) 1851 | clk_adjust 1852 ); 1853 debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); 1854 } 1855 1856 /* DDR Initialization Address (DDR_INIT_ADDR) */ 1857 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) 1858 { 1859 unsigned int init_addr = 0; /* Initialization address */ 1860 1861 ddr->ddr_init_addr = init_addr; 1862 } 1863 1864 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */ 1865 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) 1866 { 1867 unsigned int uia = 0; /* Use initialization address */ 1868 unsigned int init_ext_addr = 0; /* Initialization address */ 1869 1870 ddr->ddr_init_ext_addr = (0 1871 | ((uia & 0x1) << 31) 1872 | (init_ext_addr & 0xF) 1873 ); 1874 } 1875 1876 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */ 1877 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, 1878 const memctl_options_t *popts) 1879 { 1880 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */ 1881 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */ 1882 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */ 1883 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */ 1884 unsigned int trwt_mclk = 0; /* ext_rwt */ 1885 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */ 1886 1887 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 1888 if (popts->burst_length == DDR_BL8) { 1889 /* We set BL/2 for fixed BL8 */ 1890 rrt = 0; /* BL/2 clocks */ 1891 wwt = 0; /* BL/2 clocks */ 1892 } else { 1893 /* We need to set BL/2 + 2 to BC4 and OTF */ 1894 rrt = 2; /* BL/2 + 2 clocks */ 1895 wwt = 2; /* BL/2 + 2 clocks */ 1896 } 1897 #endif 1898 #ifdef CONFIG_SYS_FSL_DDR4 1899 dll_lock = 2; /* tDLLK = 1024 clocks */ 1900 #elif defined(CONFIG_SYS_FSL_DDR3) 1901 dll_lock = 1; /* tDLLK = 512 clocks from spec */ 1902 #endif 1903 1904 if (popts->trwt_override) 1905 trwt_mclk = popts->trwt; 1906 1907 ddr->timing_cfg_4 = (0 1908 | ((rwt & 0xf) << 28) 1909 | ((wrt & 0xf) << 24) 1910 | ((rrt & 0xf) << 20) 1911 | ((wwt & 0xf) << 16) 1912 | ((trwt_mclk & 0xc) << 12) 1913 | (dll_lock & 0x3) 1914 ); 1915 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4); 1916 } 1917 1918 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */ 1919 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) 1920 { 1921 unsigned int rodt_on = 0; /* Read to ODT on */ 1922 unsigned int rodt_off = 0; /* Read to ODT off */ 1923 unsigned int wodt_on = 0; /* Write to ODT on */ 1924 unsigned int wodt_off = 0; /* Write to ODT off */ 1925 1926 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) 1927 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1928 ((ddr->timing_cfg_2 & 0x00040000) >> 14); 1929 /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */ 1930 if (cas_latency >= wr_lat) 1931 rodt_on = cas_latency - wr_lat + 1; 1932 rodt_off = 4; /* 4 clocks */ 1933 wodt_on = 1; /* 1 clocks */ 1934 wodt_off = 4; /* 4 clocks */ 1935 #endif 1936 1937 ddr->timing_cfg_5 = (0 1938 | ((rodt_on & 0x1f) << 24) 1939 | ((rodt_off & 0x7) << 20) 1940 | ((wodt_on & 0x1f) << 12) 1941 | ((wodt_off & 0x7) << 8) 1942 ); 1943 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); 1944 } 1945 1946 #ifdef CONFIG_SYS_FSL_DDR4 1947 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) 1948 { 1949 unsigned int hs_caslat = 0; 1950 unsigned int hs_wrlat = 0; 1951 unsigned int hs_wrrec = 0; 1952 unsigned int hs_clkadj = 0; 1953 unsigned int hs_wrlvl_start = 0; 1954 1955 ddr->timing_cfg_6 = (0 1956 | ((hs_caslat & 0x1f) << 24) 1957 | ((hs_wrlat & 0x1f) << 19) 1958 | ((hs_wrrec & 0x1f) << 12) 1959 | ((hs_clkadj & 0x1f) << 6) 1960 | ((hs_wrlvl_start & 0x1f) << 0) 1961 ); 1962 debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); 1963 } 1964 1965 static void set_timing_cfg_7(const unsigned int ctrl_num, 1966 fsl_ddr_cfg_regs_t *ddr, 1967 const common_timing_params_t *common_dimm) 1968 { 1969 unsigned int txpr, tcksre, tcksrx; 1970 unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd; 1971 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); 1972 1973 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); 1974 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); 1975 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); 1976 1977 if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { 1978 if (mclk_ps >= 935) { 1979 /* parity latency 4 clocks in case of 1600/1866/2133 */ 1980 par_lat = 4; 1981 } else if (mclk_ps >= 833) { 1982 /* parity latency 5 clocks for DDR4-2400 */ 1983 par_lat = 5; 1984 } else { 1985 printf("parity: mclk_ps = %d not supported\n", mclk_ps); 1986 } 1987 } 1988 1989 cs_to_cmd = 0; 1990 1991 if (txpr <= 200) 1992 cke_rst = 0; 1993 else if (txpr <= 256) 1994 cke_rst = 1; 1995 else if (txpr <= 512) 1996 cke_rst = 2; 1997 else 1998 cke_rst = 3; 1999 2000 if (tcksre <= 19) 2001 cksre = tcksre - 5; 2002 else 2003 cksre = 15; 2004 2005 if (tcksrx <= 19) 2006 cksrx = tcksrx - 5; 2007 else 2008 cksrx = 15; 2009 2010 ddr->timing_cfg_7 = (0 2011 | ((cke_rst & 0x3) << 28) 2012 | ((cksre & 0xf) << 24) 2013 | ((cksrx & 0xf) << 20) 2014 | ((par_lat & 0xf) << 16) 2015 | ((cs_to_cmd & 0xf) << 4) 2016 ); 2017 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); 2018 } 2019 2020 static void set_timing_cfg_8(const unsigned int ctrl_num, 2021 fsl_ddr_cfg_regs_t *ddr, 2022 const memctl_options_t *popts, 2023 const common_timing_params_t *common_dimm, 2024 unsigned int cas_latency) 2025 { 2026 unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; 2027 unsigned int acttoact_bg, wrtord_bg, pre_all_rec; 2028 unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); 2029 unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 2030 ((ddr->timing_cfg_2 & 0x00040000) >> 14); 2031 2032 rwt_bg = cas_latency + 2 + 4 - wr_lat; 2033 if (rwt_bg < tccdl) 2034 rwt_bg = tccdl - rwt_bg; 2035 else 2036 rwt_bg = 0; 2037 2038 wrt_bg = wr_lat + 4 + 1 - cas_latency; 2039 if (wrt_bg < tccdl) 2040 wrt_bg = tccdl - wrt_bg; 2041 else 2042 wrt_bg = 0; 2043 2044 if (popts->burst_length == DDR_BL8) { 2045 rrt_bg = tccdl - 4; 2046 wwt_bg = tccdl - 4; 2047 } else { 2048 rrt_bg = tccdl - 2; 2049 wwt_bg = tccdl - 2; 2050 } 2051 2052 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps); 2053 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500)); 2054 if (popts->otf_burst_chop_en) 2055 wrtord_bg += 2; 2056 2057 pre_all_rec = 0; 2058 2059 ddr->timing_cfg_8 = (0 2060 | ((rwt_bg & 0xf) << 28) 2061 | ((wrt_bg & 0xf) << 24) 2062 | ((rrt_bg & 0xf) << 20) 2063 | ((wwt_bg & 0xf) << 16) 2064 | ((acttoact_bg & 0xf) << 12) 2065 | ((wrtord_bg & 0xf) << 8) 2066 | ((pre_all_rec & 0x1f) << 0) 2067 ); 2068 2069 debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8); 2070 } 2071 2072 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr) 2073 { 2074 ddr->timing_cfg_9 = 0; 2075 debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9); 2076 } 2077 2078 /* This function needs to be called after set_ddr_sdram_cfg() is called */ 2079 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, 2080 const dimm_params_t *dimm_params) 2081 { 2082 unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1; 2083 int i; 2084 2085 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { 2086 if (dimm_params[i].n_ranks) 2087 break; 2088 } 2089 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) { 2090 puts("DDR error: no DIMM found!\n"); 2091 return; 2092 } 2093 2094 ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) | 2095 ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) | 2096 ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) | 2097 ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) | 2098 ((dimm_params[i].dq_mapping[4] & 0x3F) << 2); 2099 2100 ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) | 2101 ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) | 2102 ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) | 2103 ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) | 2104 ((dimm_params[i].dq_mapping[11] & 0x3F) << 2); 2105 2106 ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) | 2107 ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) | 2108 ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) | 2109 ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) | 2110 ((dimm_params[i].dq_mapping[16] & 0x3F) << 2); 2111 2112 /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */ 2113 ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) | 2114 ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) | 2115 (acc_ecc_en ? 0 : 2116 (dimm_params[i].dq_mapping[9] & 0x3F) << 14) | 2117 dimm_params[i].dq_mapping_ors; 2118 2119 debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0); 2120 debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1); 2121 debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2); 2122 debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3); 2123 } 2124 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, 2125 const memctl_options_t *popts) 2126 { 2127 int rd_pre; 2128 2129 rd_pre = popts->quad_rank_present ? 1 : 0; 2130 2131 ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16; 2132 2133 debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3); 2134 } 2135 #endif /* CONFIG_SYS_FSL_DDR4 */ 2136 2137 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */ 2138 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) 2139 { 2140 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */ 2141 /* Normal Operation Full Calibration Time (tZQoper) */ 2142 unsigned int zqoper = 0; 2143 /* Normal Operation Short Calibration Time (tZQCS) */ 2144 unsigned int zqcs = 0; 2145 #ifdef CONFIG_SYS_FSL_DDR4 2146 unsigned int zqcs_init; 2147 #endif 2148 2149 if (zq_en) { 2150 #ifdef CONFIG_SYS_FSL_DDR4 2151 zqinit = 10; /* 1024 clocks */ 2152 zqoper = 9; /* 512 clocks */ 2153 zqcs = 7; /* 128 clocks */ 2154 zqcs_init = 5; /* 1024 refresh sequences */ 2155 #else 2156 zqinit = 9; /* 512 clocks */ 2157 zqoper = 8; /* 256 clocks */ 2158 zqcs = 6; /* 64 clocks */ 2159 #endif 2160 } 2161 2162 ddr->ddr_zq_cntl = (0 2163 | ((zq_en & 0x1) << 31) 2164 | ((zqinit & 0xF) << 24) 2165 | ((zqoper & 0xF) << 16) 2166 | ((zqcs & 0xF) << 8) 2167 #ifdef CONFIG_SYS_FSL_DDR4 2168 | ((zqcs_init & 0xF) << 0) 2169 #endif 2170 ); 2171 debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl); 2172 } 2173 2174 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ 2175 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, 2176 const memctl_options_t *popts) 2177 { 2178 /* 2179 * First DQS pulse rising edge after margining mode 2180 * is programmed (tWL_MRD) 2181 */ 2182 unsigned int wrlvl_mrd = 0; 2183 /* ODT delay after margining mode is programmed (tWL_ODTEN) */ 2184 unsigned int wrlvl_odten = 0; 2185 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */ 2186 unsigned int wrlvl_dqsen = 0; 2187 /* WRLVL_SMPL: Write leveling sample time */ 2188 unsigned int wrlvl_smpl = 0; 2189 /* WRLVL_WLR: Write leveling repeition time */ 2190 unsigned int wrlvl_wlr = 0; 2191 /* WRLVL_START: Write leveling start time */ 2192 unsigned int wrlvl_start = 0; 2193 2194 /* suggest enable write leveling for DDR3 due to fly-by topology */ 2195 if (wrlvl_en) { 2196 /* tWL_MRD min = 40 nCK, we set it 64 */ 2197 wrlvl_mrd = 0x6; 2198 /* tWL_ODTEN 128 */ 2199 wrlvl_odten = 0x7; 2200 /* tWL_DQSEN min = 25 nCK, we set it 32 */ 2201 wrlvl_dqsen = 0x5; 2202 /* 2203 * Write leveling sample time at least need 6 clocks 2204 * higher than tWLO to allow enough time for progagation 2205 * delay and sampling the prime data bits. 2206 */ 2207 wrlvl_smpl = 0xf; 2208 /* 2209 * Write leveling repetition time 2210 * at least tWLO + 6 clocks clocks 2211 * we set it 64 2212 */ 2213 wrlvl_wlr = 0x6; 2214 /* 2215 * Write leveling start time 2216 * The value use for the DQS_ADJUST for the first sample 2217 * when write leveling is enabled. It probably needs to be 2218 * overridden per platform. 2219 */ 2220 wrlvl_start = 0x8; 2221 /* 2222 * Override the write leveling sample and start time 2223 * according to specific board 2224 */ 2225 if (popts->wrlvl_override) { 2226 wrlvl_smpl = popts->wrlvl_sample; 2227 wrlvl_start = popts->wrlvl_start; 2228 } 2229 } 2230 2231 ddr->ddr_wrlvl_cntl = (0 2232 | ((wrlvl_en & 0x1) << 31) 2233 | ((wrlvl_mrd & 0x7) << 24) 2234 | ((wrlvl_odten & 0x7) << 20) 2235 | ((wrlvl_dqsen & 0x7) << 16) 2236 | ((wrlvl_smpl & 0xf) << 12) 2237 | ((wrlvl_wlr & 0x7) << 8) 2238 | ((wrlvl_start & 0x1F) << 0) 2239 ); 2240 debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl); 2241 ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2; 2242 debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2); 2243 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; 2244 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); 2245 2246 } 2247 2248 /* DDR Self Refresh Counter (DDR_SR_CNTR) */ 2249 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) 2250 { 2251 /* Self Refresh Idle Threshold */ 2252 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16; 2253 } 2254 2255 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) 2256 { 2257 if (popts->addr_hash) { 2258 ddr->ddr_eor = 0x40000000; /* address hash enable */ 2259 puts("Address hashing enabled.\n"); 2260 } 2261 } 2262 2263 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) 2264 { 2265 ddr->ddr_cdr1 = popts->ddr_cdr1; 2266 debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1); 2267 } 2268 2269 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) 2270 { 2271 ddr->ddr_cdr2 = popts->ddr_cdr2; 2272 debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2); 2273 } 2274 2275 unsigned int 2276 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) 2277 { 2278 unsigned int res = 0; 2279 2280 /* 2281 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are 2282 * not set at the same time. 2283 */ 2284 if (ddr->ddr_sdram_cfg & 0x10000000 2285 && ddr->ddr_sdram_cfg & 0x00008000) { 2286 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] " 2287 " should not be set at the same time.\n"); 2288 res++; 2289 } 2290 2291 return res; 2292 } 2293 2294 unsigned int 2295 compute_fsl_memctl_config_regs(const unsigned int ctrl_num, 2296 const memctl_options_t *popts, 2297 fsl_ddr_cfg_regs_t *ddr, 2298 const common_timing_params_t *common_dimm, 2299 const dimm_params_t *dimm_params, 2300 unsigned int dbw_cap_adj, 2301 unsigned int size_only) 2302 { 2303 unsigned int i; 2304 unsigned int cas_latency; 2305 unsigned int additive_latency; 2306 unsigned int sr_it; 2307 unsigned int zq_en; 2308 unsigned int wrlvl_en; 2309 unsigned int ip_rev = 0; 2310 unsigned int unq_mrs_en = 0; 2311 int cs_en = 1; 2312 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 2313 unsigned int ddr_freq; 2314 #endif 2315 #if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \ 2316 defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \ 2317 defined(CONFIG_SYS_FSL_ERRATUM_A009942) 2318 struct ccsr_ddr __iomem *ddrc; 2319 2320 switch (ctrl_num) { 2321 case 0: 2322 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR; 2323 break; 2324 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) 2325 case 1: 2326 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR; 2327 break; 2328 #endif 2329 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) 2330 case 2: 2331 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR; 2332 break; 2333 #endif 2334 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) 2335 case 3: 2336 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR; 2337 break; 2338 #endif 2339 default: 2340 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num); 2341 return 1; 2342 } 2343 #endif 2344 2345 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t)); 2346 2347 if (common_dimm == NULL) { 2348 printf("Error: subset DIMM params struct null pointer\n"); 2349 return 1; 2350 } 2351 2352 /* 2353 * Process overrides first. 2354 * 2355 * FIXME: somehow add dereated caslat to this 2356 */ 2357 cas_latency = (popts->cas_latency_override) 2358 ? popts->cas_latency_override_value 2359 : common_dimm->lowest_common_spd_caslat; 2360 2361 additive_latency = (popts->additive_latency_override) 2362 ? popts->additive_latency_override_value 2363 : common_dimm->additive_latency; 2364 2365 sr_it = (popts->auto_self_refresh_en) 2366 ? popts->sr_it 2367 : 0; 2368 /* ZQ calibration */ 2369 zq_en = (popts->zq_en) ? 1 : 0; 2370 /* write leveling */ 2371 wrlvl_en = (popts->wrlvl_en) ? 1 : 0; 2372 2373 /* Chip Select Memory Bounds (CSn_BNDS) */ 2374 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { 2375 unsigned long long ea, sa; 2376 unsigned int cs_per_dimm 2377 = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR; 2378 unsigned int dimm_number 2379 = i / cs_per_dimm; 2380 unsigned long long rank_density 2381 = dimm_params[dimm_number].rank_density >> dbw_cap_adj; 2382 2383 if (dimm_params[dimm_number].n_ranks == 0) { 2384 debug("Skipping setup of CS%u " 2385 "because n_ranks on DIMM %u is 0\n", i, dimm_number); 2386 continue; 2387 } 2388 if (popts->memctl_interleaving) { 2389 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { 2390 case FSL_DDR_CS0_CS1_CS2_CS3: 2391 break; 2392 case FSL_DDR_CS0_CS1: 2393 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 2394 if (i > 1) 2395 cs_en = 0; 2396 break; 2397 case FSL_DDR_CS2_CS3: 2398 default: 2399 if (i > 0) 2400 cs_en = 0; 2401 break; 2402 } 2403 sa = common_dimm->base_address; 2404 ea = sa + common_dimm->total_mem - 1; 2405 } else if (!popts->memctl_interleaving) { 2406 /* 2407 * If memory interleaving between controllers is NOT 2408 * enabled, the starting address for each memory 2409 * controller is distinct. However, because rank 2410 * interleaving is enabled, the starting and ending 2411 * addresses of the total memory on that memory 2412 * controller needs to be programmed into its 2413 * respective CS0_BNDS. 2414 */ 2415 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) { 2416 case FSL_DDR_CS0_CS1_CS2_CS3: 2417 sa = common_dimm->base_address; 2418 ea = sa + common_dimm->total_mem - 1; 2419 break; 2420 case FSL_DDR_CS0_CS1_AND_CS2_CS3: 2421 if ((i >= 2) && (dimm_number == 0)) { 2422 sa = dimm_params[dimm_number].base_address + 2423 2 * rank_density; 2424 ea = sa + 2 * rank_density - 1; 2425 } else { 2426 sa = dimm_params[dimm_number].base_address; 2427 ea = sa + 2 * rank_density - 1; 2428 } 2429 break; 2430 case FSL_DDR_CS0_CS1: 2431 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { 2432 sa = dimm_params[dimm_number].base_address; 2433 ea = sa + rank_density - 1; 2434 if (i != 1) 2435 sa += (i % cs_per_dimm) * rank_density; 2436 ea += (i % cs_per_dimm) * rank_density; 2437 } else { 2438 sa = 0; 2439 ea = 0; 2440 } 2441 if (i == 0) 2442 ea += rank_density; 2443 break; 2444 case FSL_DDR_CS2_CS3: 2445 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { 2446 sa = dimm_params[dimm_number].base_address; 2447 ea = sa + rank_density - 1; 2448 if (i != 3) 2449 sa += (i % cs_per_dimm) * rank_density; 2450 ea += (i % cs_per_dimm) * rank_density; 2451 } else { 2452 sa = 0; 2453 ea = 0; 2454 } 2455 if (i == 2) 2456 ea += (rank_density >> dbw_cap_adj); 2457 break; 2458 default: /* No bank(chip-select) interleaving */ 2459 sa = dimm_params[dimm_number].base_address; 2460 ea = sa + rank_density - 1; 2461 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) { 2462 sa += (i % cs_per_dimm) * rank_density; 2463 ea += (i % cs_per_dimm) * rank_density; 2464 } else { 2465 sa = 0; 2466 ea = 0; 2467 } 2468 break; 2469 } 2470 } 2471 2472 sa >>= 24; 2473 ea >>= 24; 2474 2475 if (cs_en) { 2476 ddr->cs[i].bnds = (0 2477 | ((sa & 0xffff) << 16) /* starting address */ 2478 | ((ea & 0xffff) << 0) /* ending address */ 2479 ); 2480 } else { 2481 /* setting bnds to 0xffffffff for inactive CS */ 2482 ddr->cs[i].bnds = 0xffffffff; 2483 } 2484 2485 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); 2486 set_csn_config(dimm_number, i, ddr, popts, dimm_params); 2487 set_csn_config_2(i, ddr); 2488 } 2489 2490 /* 2491 * In the case we only need to compute the ddr sdram size, we only need 2492 * to set csn registers, so return from here. 2493 */ 2494 if (size_only) 2495 return 0; 2496 2497 set_ddr_eor(ddr, popts); 2498 2499 #if !defined(CONFIG_SYS_FSL_DDR1) 2500 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); 2501 #endif 2502 2503 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, 2504 additive_latency); 2505 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); 2506 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, 2507 cas_latency, additive_latency); 2508 2509 set_ddr_cdr1(ddr, popts); 2510 set_ddr_cdr2(ddr, popts); 2511 set_ddr_sdram_cfg(ddr, popts, common_dimm); 2512 ip_rev = fsl_ddr_get_version(ctrl_num); 2513 if (ip_rev > 0x40400) 2514 unq_mrs_en = 1; 2515 2516 if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) 2517 ddr->debug[18] = popts->cswl_override; 2518 2519 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); 2520 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, 2521 cas_latency, additive_latency, unq_mrs_en); 2522 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); 2523 #ifdef CONFIG_SYS_FSL_DDR4 2524 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); 2525 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); 2526 #endif 2527 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); 2528 set_ddr_data_init(ddr); 2529 set_ddr_sdram_clk_cntl(ddr, popts); 2530 set_ddr_init_addr(ddr); 2531 set_ddr_init_ext_addr(ddr); 2532 set_timing_cfg_4(ddr, popts); 2533 set_timing_cfg_5(ddr, cas_latency); 2534 #ifdef CONFIG_SYS_FSL_DDR4 2535 set_ddr_sdram_cfg_3(ddr, popts); 2536 set_timing_cfg_6(ddr); 2537 set_timing_cfg_7(ctrl_num, ddr, common_dimm); 2538 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); 2539 set_timing_cfg_9(ddr); 2540 set_ddr_dq_mapping(ddr, dimm_params); 2541 #endif 2542 2543 set_ddr_zq_cntl(ddr, zq_en); 2544 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); 2545 2546 set_ddr_sr_cntr(ddr, sr_it); 2547 2548 set_ddr_sdram_rcw(ddr, popts, common_dimm); 2549 2550 #ifdef CONFIG_SYS_FSL_DDR_EMU 2551 /* disble DDR training for emulator */ 2552 ddr->debug[2] = 0x00000400; 2553 ddr->debug[4] = 0xff800800; 2554 ddr->debug[5] = 0x08000800; 2555 ddr->debug[6] = 0x08000800; 2556 ddr->debug[7] = 0x08000800; 2557 ddr->debug[8] = 0x08000800; 2558 #endif 2559 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508 2560 if ((ip_rev >= 0x40000) && (ip_rev < 0x40400)) 2561 ddr->debug[2] |= 0x00000200; /* set bit 22 */ 2562 #endif 2563 2564 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4) 2565 /* Erratum applies when accumulated ECC is used, or DBI is enabled */ 2566 #define IS_ACC_ECC_EN(v) ((v) & 0x4) 2567 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2) 2568 if (has_erratum_a008378()) { 2569 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) || 2570 IS_DBI(ddr->ddr_sdram_cfg_3)) { 2571 ddr->debug[28] = ddr_in32(&ddrc->debug[28]); 2572 ddr->debug[28] |= (0x9 << 20); 2573 } 2574 } 2575 #endif 2576 2577 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 2578 ddr_freq = get_ddr_freq(ctrl_num) / 1000000; 2579 ddr->debug[28] |= ddr_in32(&ddrc->debug[28]); 2580 ddr->debug[28] &= 0xff0fff00; 2581 if (ddr_freq <= 1333) 2582 ddr->debug[28] |= 0x0080006a; 2583 else if (ddr_freq <= 1600) 2584 ddr->debug[28] |= 0x0070006f; 2585 else if (ddr_freq <= 1867) 2586 ddr->debug[28] |= 0x00700076; 2587 else if (ddr_freq <= 2133) 2588 ddr->debug[28] |= 0x0060007b; 2589 if (popts->cpo_sample) 2590 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) | 2591 popts->cpo_sample; 2592 #endif 2593 2594 return check_fsl_memctl_config_regs(ddr); 2595 } 2596 2597 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942 2598 /* 2599 * This additional workaround of A009942 checks the condition to determine if 2600 * the CPO value set by the existing A009942 workaround needs to be updated. 2601 * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with 2602 * expected optimal value, the optimal value is highly board dependent. 2603 */ 2604 void erratum_a009942_check_cpo(void) 2605 { 2606 struct ccsr_ddr __iomem *ddr = 2607 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); 2608 u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal; 2609 u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; 2610 u32 cpo_max = cpo_min; 2611 u32 sdram_cfg, i, tmp, lanes, ddr_type; 2612 bool update_cpo = false, has_ecc = false; 2613 2614 sdram_cfg = ddr_in32(&ddr->sdram_cfg); 2615 if (sdram_cfg & SDRAM_CFG_32_BE) 2616 lanes = 4; 2617 else if (sdram_cfg & SDRAM_CFG_16_BE) 2618 lanes = 2; 2619 else 2620 lanes = 8; 2621 2622 if (sdram_cfg & SDRAM_CFG_ECC_EN) 2623 has_ecc = true; 2624 2625 /* determine the maximum and minimum CPO values */ 2626 for (i = 9; i < 9 + lanes / 2; i++) { 2627 cpo = ddr_in32(&ddr->debug[i]); 2628 cpo_e = cpo >> 24; 2629 cpo_o = (cpo >> 8) & 0xff; 2630 tmp = min(cpo_e, cpo_o); 2631 if (tmp < cpo_min) 2632 cpo_min = tmp; 2633 tmp = max(cpo_e, cpo_o); 2634 if (tmp > cpo_max) 2635 cpo_max = tmp; 2636 } 2637 2638 if (has_ecc) { 2639 cpo = ddr_in32(&ddr->debug[13]); 2640 cpo = cpo >> 24; 2641 if (cpo < cpo_min) 2642 cpo_min = cpo; 2643 if (cpo > cpo_max) 2644 cpo_max = cpo; 2645 } 2646 2647 cpo_target = ddr_in32(&ddr->debug[28]) & 0xff; 2648 cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27; 2649 debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal, 2650 cpo_target); 2651 debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min); 2652 2653 ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> 2654 SDRAM_CFG_SDRAM_TYPE_SHIFT; 2655 if (ddr_type == SDRAM_TYPE_DDR4) 2656 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false; 2657 else if (ddr_type == SDRAM_TYPE_DDR3) 2658 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false; 2659 2660 if (update_cpo) { 2661 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal); 2662 printf("in <board>/ddr.c to optimize cpo\n"); 2663 } 2664 } 2665 #endif 2666