1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <clk.h> 8 #include <crypto.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/clock.h> 13 #include <rockchip/crypto_hash_cache.h> 14 #include <rockchip/crypto_v2.h> 15 #include <rockchip/crypto_v2_pka.h> 16 17 #define RK_HASH_CTX_MAGIC 0x1A1A1A1A 18 19 #define CRYPTO_TRNG_MAX 32 20 21 enum endian_mode { 22 BIG_ENDIAN = 0, 23 LITTLE_ENDIAN 24 }; 25 26 enum clk_type { 27 CLK = 0, 28 HCLK 29 }; 30 31 struct crypto_lli_desc { 32 u32 src_addr; 33 u32 src_len; 34 u32 dst_addr; 35 u32 dst_len; 36 u32 user_define; 37 u32 reserve; 38 u32 dma_ctrl; 39 u32 next_addr; 40 }; 41 42 struct rk_hash_ctx { 43 struct crypto_lli_desc data_lli; /* lli desc */ 44 struct crypto_hash_cache *hash_cache; 45 u32 magic; /* to check ctx */ 46 u32 algo; /* hash algo */ 47 u8 digest_size; /* hash out length */ 48 u8 reserved[3]; 49 }; 50 51 struct rockchip_crypto_priv { 52 fdt_addr_t reg; 53 struct clk clk; 54 u32 frequency; 55 char *clocks; 56 u32 *frequencies; 57 u32 nclocks; 58 u32 length; 59 struct rk_hash_ctx *hw_ctx; 60 }; 61 62 #define LLI_ADDR_ALIGIN_SIZE 8 63 #define DATA_ADDR_ALIGIN_SIZE 8 64 #define DATA_LEN_ALIGIN_SIZE 64 65 66 /* crypto timeout 500ms, must support more than 32M data per times*/ 67 #define HASH_UPDATE_LIMIT (32 * 1024 * 1024) 68 #define RK_CRYPTO_TIME_OUT 500000 69 70 #define RK_WHILE_TIME_OUT(condition, timeout, ret) { \ 71 u32 time_out = timeout; \ 72 ret = 0; \ 73 while (condition) { \ 74 if (time_out-- == 0) { \ 75 debug("[%s] %d: time out!\n", __func__,\ 76 __LINE__); \ 77 ret = -ETIME; \ 78 break; \ 79 } \ 80 udelay(1); \ 81 } \ 82 } while (0) 83 84 typedef u32 paddr_t; 85 #define virt_to_phys(addr) (((unsigned long)addr) & 0xffffffff) 86 #define phys_to_virt(addr, area) ((unsigned long)addr) 87 88 fdt_addr_t crypto_base; 89 90 static void word2byte(u32 word, u8 *ch, u32 endian) 91 { 92 /* 0: Big-Endian 1: Little-Endian */ 93 if (endian == BIG_ENDIAN) { 94 ch[0] = (word >> 24) & 0xff; 95 ch[1] = (word >> 16) & 0xff; 96 ch[2] = (word >> 8) & 0xff; 97 ch[3] = (word >> 0) & 0xff; 98 } else if (endian == LITTLE_ENDIAN) { 99 ch[0] = (word >> 0) & 0xff; 100 ch[1] = (word >> 8) & 0xff; 101 ch[2] = (word >> 16) & 0xff; 102 ch[3] = (word >> 24) & 0xff; 103 } else { 104 ch[0] = 0; 105 ch[1] = 0; 106 ch[2] = 0; 107 ch[3] = 0; 108 } 109 } 110 111 static inline void clear_hash_out_reg(void) 112 { 113 int i; 114 115 /*clear out register*/ 116 for (i = 0; i < 16; i++) 117 crypto_write(0, CRYPTO_HASH_DOUT_0 + 4 * i); 118 } 119 120 static int hw_crypto_reset(void) 121 { 122 u32 tmp = 0, tmp_mask = 0; 123 int ret; 124 125 tmp = CRYPTO_SW_PKA_RESET | CRYPTO_SW_CC_RESET; 126 tmp_mask = tmp << CRYPTO_WRITE_MASK_SHIFT; 127 128 /* reset pka and crypto modules*/ 129 crypto_write(tmp | tmp_mask, CRYPTO_RST_CTL); 130 131 /* wait reset compelete */ 132 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RST_CTL), 133 RK_CRYPTO_TIME_OUT, ret); 134 return ret; 135 } 136 137 static void hw_hash_clean_ctx(struct rk_hash_ctx *ctx) 138 { 139 /* clear hash status */ 140 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 141 142 assert(ctx); 143 assert(ctx->magic == RK_HASH_CTX_MAGIC); 144 145 crypto_hash_cache_free(ctx->hash_cache); 146 147 memset(ctx, 0x00, sizeof(*ctx)); 148 } 149 150 static int rk_hash_init(void *hw_ctx, u32 algo) 151 { 152 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)hw_ctx; 153 u32 reg_ctrl = 0; 154 int ret; 155 156 if (!tmp_ctx) 157 return -EINVAL; 158 159 reg_ctrl = CRYPTO_SW_CC_RESET; 160 crypto_write(reg_ctrl | (reg_ctrl << CRYPTO_WRITE_MASK_SHIFT), 161 CRYPTO_RST_CTL); 162 163 /* wait reset compelete */ 164 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RST_CTL), 165 RK_CRYPTO_TIME_OUT, ret); 166 167 reg_ctrl = 0; 168 tmp_ctx->algo = algo; 169 switch (algo) { 170 case CRYPTO_MD5: 171 reg_ctrl |= CRYPTO_MODE_MD5; 172 tmp_ctx->digest_size = 16; 173 break; 174 case CRYPTO_SHA1: 175 reg_ctrl |= CRYPTO_MODE_SHA1; 176 tmp_ctx->digest_size = 20; 177 break; 178 case CRYPTO_SHA256: 179 reg_ctrl |= CRYPTO_MODE_SHA256; 180 tmp_ctx->digest_size = 32; 181 break; 182 case CRYPTO_SHA512: 183 reg_ctrl |= CRYPTO_MODE_SHA512; 184 tmp_ctx->digest_size = 64; 185 break; 186 187 default: 188 ret = -EINVAL; 189 goto exit; 190 } 191 192 clear_hash_out_reg(); 193 194 /* enable hardware padding */ 195 reg_ctrl |= CRYPTO_HW_PAD_ENABLE; 196 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_HASH_CTL); 197 198 /* FIFO input and output data byte swap */ 199 /* such as B0, B1, B2, B3 -> B3, B2, B1, B0 */ 200 reg_ctrl = CRYPTO_DOUT_BYTESWAP | CRYPTO_DOIN_BYTESWAP; 201 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_FIFO_CTL); 202 203 /* enable src_item_done interrupt */ 204 crypto_write(CRYPTO_SRC_ITEM_INT_EN, CRYPTO_DMA_INT_EN); 205 206 tmp_ctx->magic = RK_HASH_CTX_MAGIC; 207 208 return 0; 209 exit: 210 /* clear hash setting if init failed */ 211 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 212 213 return ret; 214 } 215 216 static int rk_hash_direct_calc(void *hw_data, const u8 *data, 217 u32 data_len, u8 *started_flag, u8 is_last) 218 { 219 struct rockchip_crypto_priv *priv = hw_data; 220 struct rk_hash_ctx *hash_ctx = priv->hw_ctx; 221 struct crypto_lli_desc *lli = &hash_ctx->data_lli; 222 int ret = -EINVAL; 223 u32 tmp = 0; 224 225 assert(IS_ALIGNED((ulong)data, DATA_ADDR_ALIGIN_SIZE)); 226 assert(is_last || IS_ALIGNED(data_len, DATA_LEN_ALIGIN_SIZE)); 227 228 debug("%s: data = %p, len = %u, s = %x, l = %x\n", 229 __func__, data, data_len, *started_flag, is_last); 230 231 memset(lli, 0x00, sizeof(*lli)); 232 lli->src_addr = (u32)virt_to_phys(data); 233 lli->src_len = data_len; 234 lli->dma_ctrl = LLI_DMA_CTRL_SRC_DONE; 235 236 if (is_last) { 237 lli->user_define |= LLI_USER_STRING_LAST; 238 lli->dma_ctrl |= LLI_DMA_CTRL_LAST; 239 } else { 240 lli->next_addr = (u32)virt_to_phys(lli); 241 lli->dma_ctrl |= LLI_DMA_CTRL_PAUSE; 242 } 243 244 if (!(*started_flag)) { 245 lli->user_define |= 246 (LLI_USER_STRING_START | LLI_USER_CPIHER_START); 247 crypto_write((u32)virt_to_phys(lli), CRYPTO_DMA_LLI_ADDR); 248 crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) | 249 CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL); 250 tmp = CRYPTO_DMA_START; 251 *started_flag = 1; 252 } else { 253 tmp = CRYPTO_DMA_RESTART; 254 } 255 256 /* flush cache */ 257 crypto_flush_cacheline((ulong)lli, sizeof(*lli)); 258 crypto_flush_cacheline((ulong)data, data_len); 259 260 /* start calculate */ 261 crypto_write(tmp << CRYPTO_WRITE_MASK_SHIFT | tmp, 262 CRYPTO_DMA_CTL); 263 264 /* wait calc ok */ 265 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_DMA_INT_ST), 266 RK_CRYPTO_TIME_OUT, ret); 267 268 /* clear interrupt status */ 269 tmp = crypto_read(CRYPTO_DMA_INT_ST); 270 crypto_write(tmp, CRYPTO_DMA_INT_ST); 271 272 if (tmp != CRYPTO_SRC_ITEM_DONE_INT_ST && 273 tmp != CRYPTO_ZERO_LEN_INT_ST) { 274 debug("[%s] %d: CRYPTO_DMA_INT_ST = 0x%x\n", 275 __func__, __LINE__, tmp); 276 goto exit; 277 } 278 279 priv->length += data_len; 280 exit: 281 return ret; 282 } 283 284 int rk_hash_update(void *ctx, const u8 *data, u32 data_len) 285 { 286 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 287 int ret = -EINVAL; 288 289 debug("\n"); 290 if (!tmp_ctx || !data) 291 goto exit; 292 293 if (tmp_ctx->digest_size == 0 || tmp_ctx->magic != RK_HASH_CTX_MAGIC) 294 goto exit; 295 296 ret = crypto_hash_update_with_cache(tmp_ctx->hash_cache, 297 data, data_len); 298 299 exit: 300 /* free lli list */ 301 if (ret) 302 hw_hash_clean_ctx(tmp_ctx); 303 304 return ret; 305 } 306 307 int rk_hash_final(void *ctx, u8 *digest, size_t len) 308 { 309 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 310 int ret = -EINVAL; 311 u32 i; 312 313 if (!digest) 314 goto exit; 315 316 if (!tmp_ctx || 317 tmp_ctx->digest_size == 0 || 318 len > tmp_ctx->digest_size || 319 tmp_ctx->magic != RK_HASH_CTX_MAGIC) { 320 goto exit; 321 } 322 323 /* wait hash value ok */ 324 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_HASH_VALID), 325 RK_CRYPTO_TIME_OUT, ret); 326 327 for (i = 0; i < len / 4; i++) 328 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 329 digest + i * 4, BIG_ENDIAN); 330 331 if (len % 4) { 332 u8 tmp_buf[4]; 333 334 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 335 tmp_buf, BIG_ENDIAN); 336 memcpy(digest + i * 4, tmp_buf, len % 4); 337 } 338 339 /* clear hash status */ 340 crypto_write(CRYPTO_HASH_IS_VALID, CRYPTO_HASH_VALID); 341 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 342 343 exit: 344 345 return ret; 346 } 347 348 static int rk_trng(u8 *trng, u32 len) 349 { 350 u32 i, reg_ctrl = 0; 351 int ret = -EINVAL; 352 u32 buf[8]; 353 354 if (len > CRYPTO_TRNG_MAX) 355 return -EINVAL; 356 357 memset(buf, 0, sizeof(buf)); 358 359 /* enable osc_ring to get entropy, sample period is set as 50 */ 360 crypto_write(50, CRYPTO_RNG_SAMPLE_CNT); 361 362 reg_ctrl |= CRYPTO_RNG_256_bit_len; 363 reg_ctrl |= CRYPTO_RNG_SLOWER_SOC_RING_1; 364 reg_ctrl |= CRYPTO_RNG_ENABLE; 365 reg_ctrl |= CRYPTO_RNG_START; 366 reg_ctrl |= CRYPTO_WRITE_MASK_ALL; 367 368 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_RNG_CTL); 369 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RNG_CTL) & CRYPTO_RNG_START, 370 RK_CRYPTO_TIME_OUT, ret); 371 372 if (ret == 0) { 373 for (i = 0; i < ARRAY_SIZE(buf); i++) 374 buf[i] = crypto_read(CRYPTO_RNG_DOUT_0 + i * 4); 375 memcpy(trng, buf, len); 376 } 377 378 /* close TRNG */ 379 crypto_write(0 | CRYPTO_WRITE_MASK_ALL, CRYPTO_RNG_CTL); 380 381 return ret; 382 } 383 384 static u32 rockchip_crypto_capability(struct udevice *dev) 385 { 386 return CRYPTO_MD5 | 387 CRYPTO_SHA1 | 388 CRYPTO_SHA256 | 389 #if !defined(CONFIG_ROCKCHIP_RK1808) 390 CRYPTO_SHA512 | 391 #endif 392 CRYPTO_RSA512 | 393 CRYPTO_RSA1024 | 394 CRYPTO_RSA2048 | 395 CRYPTO_RSA3072 | 396 CRYPTO_RSA4096 | 397 CRYPTO_TRNG; 398 } 399 400 static int rockchip_crypto_sha_init(struct udevice *dev, sha_context *ctx) 401 { 402 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 403 struct rk_hash_ctx *hash_ctx = priv->hw_ctx; 404 405 if (!ctx) 406 return -EINVAL; 407 408 memset(hash_ctx, 0x00, sizeof(*hash_ctx)); 409 410 priv->length = 0; 411 412 hash_ctx->hash_cache = crypto_hash_cache_alloc(rk_hash_direct_calc, 413 priv, ctx->length, 414 DATA_ADDR_ALIGIN_SIZE, 415 DATA_LEN_ALIGIN_SIZE); 416 if (!hash_ctx->hash_cache) 417 return -EFAULT; 418 419 return rk_hash_init(hash_ctx, ctx->algo); 420 } 421 422 static int rockchip_crypto_sha_update(struct udevice *dev, 423 u32 *input, u32 len) 424 { 425 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 426 int ret, i; 427 u8 *p; 428 429 if (!len) 430 return -EINVAL; 431 432 p = (u8 *)input; 433 434 for (i = 0; i < len / HASH_UPDATE_LIMIT; i++, p += HASH_UPDATE_LIMIT) { 435 ret = rk_hash_update(priv->hw_ctx, p, HASH_UPDATE_LIMIT); 436 if (ret) 437 goto exit; 438 } 439 440 if (len % HASH_UPDATE_LIMIT) 441 ret = rk_hash_update(priv->hw_ctx, p, len % HASH_UPDATE_LIMIT); 442 443 exit: 444 return ret; 445 } 446 447 static int rockchip_crypto_sha_final(struct udevice *dev, 448 sha_context *ctx, u8 *output) 449 { 450 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 451 u32 nbits; 452 int ret; 453 454 nbits = crypto_algo_nbits(ctx->algo); 455 456 if (priv->length != ctx->length) { 457 printf("total length(0x%08x) != init length(0x%08x)!\n", 458 priv->length, ctx->length); 459 ret = -EIO; 460 goto exit; 461 } 462 463 ret = rk_hash_final(priv->hw_ctx, (u8 *)output, BITS2BYTE(nbits)); 464 465 exit: 466 hw_hash_clean_ctx(priv->hw_ctx); 467 return ret; 468 } 469 470 #if CONFIG_IS_ENABLED(ROCKCHIP_RSA) 471 static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, 472 u8 *sign, u8 *output) 473 { 474 struct mpa_num *mpa_m = NULL, *mpa_e = NULL, *mpa_n = NULL; 475 struct mpa_num *mpa_c = NULL, *mpa_result = NULL; 476 u32 n_bits, n_words; 477 u32 *rsa_result; 478 int ret; 479 480 if (!ctx) 481 return -EINVAL; 482 483 if (ctx->algo != CRYPTO_RSA512 && 484 ctx->algo != CRYPTO_RSA1024 && 485 ctx->algo != CRYPTO_RSA2048 && 486 ctx->algo != CRYPTO_RSA3072 && 487 ctx->algo != CRYPTO_RSA4096) 488 return -EINVAL; 489 490 n_bits = crypto_algo_nbits(ctx->algo); 491 n_words = BITS2WORD(n_bits); 492 493 rsa_result = malloc(BITS2BYTE(n_bits)); 494 if (!rsa_result) 495 return -ENOMEM; 496 497 memset(rsa_result, 0x00, BITS2BYTE(n_bits)); 498 499 ret = rk_mpa_alloc(&mpa_m); 500 ret |= rk_mpa_alloc(&mpa_e); 501 ret |= rk_mpa_alloc(&mpa_n); 502 ret |= rk_mpa_alloc(&mpa_c); 503 ret |= rk_mpa_alloc(&mpa_result); 504 if (ret) 505 goto exit; 506 507 mpa_m->d = (void *)sign; 508 mpa_e->d = (void *)ctx->e; 509 mpa_n->d = (void *)ctx->n; 510 mpa_c->d = (void *)ctx->c; 511 mpa_result->d = (void *)rsa_result; 512 513 mpa_m->size = n_words; 514 mpa_e->size = n_words; 515 mpa_n->size = n_words; 516 mpa_c->size = n_words; 517 mpa_result->size = n_words; 518 519 ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result); 520 if (!ret) 521 memcpy(output, rsa_result, BITS2BYTE(n_bits)); 522 523 exit: 524 free(rsa_result); 525 rk_mpa_free(&mpa_m); 526 rk_mpa_free(&mpa_e); 527 rk_mpa_free(&mpa_n); 528 rk_mpa_free(&mpa_c); 529 rk_mpa_free(&mpa_result); 530 531 return ret; 532 } 533 #else 534 static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, 535 u8 *sign, u8 *output) 536 { 537 return -ENOSYS; 538 } 539 #endif 540 541 static int rockchip_crypto_get_trng(struct udevice *dev, u8 *output, u32 len) 542 { 543 int ret; 544 u32 i; 545 546 if (!dev || !output || !len) 547 return -EINVAL; 548 549 for (i = 0; i < len / CRYPTO_TRNG_MAX; i++) { 550 ret = rk_trng(output + i * CRYPTO_TRNG_MAX, CRYPTO_TRNG_MAX); 551 if (ret) 552 goto fail; 553 } 554 555 ret = rk_trng(output + i * CRYPTO_TRNG_MAX, len % CRYPTO_TRNG_MAX); 556 557 fail: 558 return ret; 559 } 560 561 static const struct dm_crypto_ops rockchip_crypto_ops = { 562 .capability = rockchip_crypto_capability, 563 .sha_init = rockchip_crypto_sha_init, 564 .sha_update = rockchip_crypto_sha_update, 565 .sha_final = rockchip_crypto_sha_final, 566 .rsa_verify = rockchip_crypto_rsa_verify, 567 .get_trng = rockchip_crypto_get_trng, 568 }; 569 570 /* 571 * Only use "clocks" to parse crypto clock id and use rockchip_get_clk(). 572 * Because we always add crypto node in U-Boot dts, when kernel dtb enabled : 573 * 574 * 1. There is cru phandle mismatch between U-Boot and kernel dtb; 575 * 2. CONFIG_OF_SPL_REMOVE_PROPS removes clock property; 576 */ 577 static int rockchip_crypto_ofdata_to_platdata(struct udevice *dev) 578 { 579 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 580 int len, ret = -EINVAL; 581 582 if (!dev_read_prop(dev, "clocks", &len)) { 583 printf("Can't find \"clocks\" property\n"); 584 return -EINVAL; 585 } 586 587 memset(priv, 0x00, sizeof(*priv)); 588 priv->clocks = malloc(len); 589 if (!priv->clocks) 590 return -ENOMEM; 591 592 priv->nclocks = len / sizeof(u32); 593 if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks, 594 priv->nclocks)) { 595 printf("Can't read \"clocks\" property\n"); 596 ret = -EINVAL; 597 goto exit; 598 } 599 600 if (!dev_read_prop(dev, "clock-frequency", &len)) { 601 printf("Can't find \"clock-frequency\" property\n"); 602 ret = -EINVAL; 603 goto exit; 604 } 605 606 priv->frequencies = malloc(len); 607 if (!priv->frequencies) { 608 ret = -ENOMEM; 609 goto exit; 610 } 611 612 priv->nclocks = len / sizeof(u32); 613 if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies, 614 priv->nclocks)) { 615 printf("Can't read \"clock-frequency\" property\n"); 616 ret = -EINVAL; 617 goto exit; 618 } 619 620 priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev); 621 622 crypto_base = priv->reg; 623 624 return 0; 625 exit: 626 if (priv->clocks) 627 free(priv->clocks); 628 629 if (priv->frequencies) 630 free(priv->frequencies); 631 632 return ret; 633 } 634 635 static int rockchip_crypto_probe(struct udevice *dev) 636 { 637 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 638 int i, ret = 0; 639 u32* clocks; 640 641 priv->hw_ctx = memalign(LLI_ADDR_ALIGIN_SIZE, 642 sizeof(struct rk_hash_ctx)); 643 if (!priv->hw_ctx) 644 return -ENOMEM; 645 646 ret = rockchip_get_clk(&priv->clk.dev); 647 if (ret) { 648 printf("Failed to get clk device, ret=%d\n", ret); 649 return ret; 650 } 651 652 clocks = (u32 *)priv->clocks; 653 for (i = 0; i < priv->nclocks; i++) { 654 priv->clk.id = clocks[i * 2 + 1]; 655 ret = clk_set_rate(&priv->clk, priv->frequencies[i]); 656 if (ret < 0) { 657 printf("%s: Failed to set clk(%ld): ret=%d\n", 658 __func__, priv->clk.id, ret); 659 return ret; 660 } 661 } 662 663 hw_crypto_reset(); 664 665 return 0; 666 } 667 668 static const struct udevice_id rockchip_crypto_ids[] = { 669 { .compatible = "rockchip,px30-crypto" }, 670 { .compatible = "rockchip,rk1808-crypto" }, 671 { .compatible = "rockchip,rk3308-crypto" }, 672 { .compatible = "rockchip,rv1126-crypto" }, 673 { } 674 }; 675 676 U_BOOT_DRIVER(rockchip_crypto_v2) = { 677 .name = "rockchip_crypto_v2", 678 .id = UCLASS_CRYPTO, 679 .of_match = rockchip_crypto_ids, 680 .ops = &rockchip_crypto_ops, 681 .probe = rockchip_crypto_probe, 682 .ofdata_to_platdata = rockchip_crypto_ofdata_to_platdata, 683 .priv_auto_alloc_size = sizeof(struct rockchip_crypto_priv), 684 }; 685