1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <clk.h> 8 #include <crypto.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/clock.h> 13 #include <rockchip/crypto_hash_cache.h> 14 #include <rockchip/crypto_v2.h> 15 #include <rockchip/crypto_v2_pka.h> 16 17 #define RK_HASH_CTX_MAGIC 0x1A1A1A1A 18 19 #define CRYPTO_TRNG_MAX 32 20 21 enum endian_mode { 22 BIG_ENDIAN = 0, 23 LITTLE_ENDIAN 24 }; 25 26 enum clk_type { 27 CLK = 0, 28 HCLK 29 }; 30 31 struct crypto_lli_desc { 32 u32 src_addr; 33 u32 src_len; 34 u32 dst_addr; 35 u32 dst_len; 36 u32 user_define; 37 u32 reserve; 38 u32 dma_ctrl; 39 u32 next_addr; 40 }; 41 42 struct rk_hash_ctx { 43 struct crypto_lli_desc data_lli; /* lli desc */ 44 struct crypto_hash_cache *hash_cache; 45 u32 magic; /* to check ctx */ 46 u32 algo; /* hash algo */ 47 u8 digest_size; /* hash out length */ 48 u8 reserved[3]; 49 }; 50 51 struct rockchip_crypto_priv { 52 fdt_addr_t reg; 53 struct clk clk; 54 u32 frequency; 55 char *clocks; 56 u32 *frequencies; 57 u32 nclocks; 58 u32 length; 59 struct rk_hash_ctx *hw_ctx; 60 }; 61 62 #define LLI_ADDR_ALIGIN_SIZE 8 63 #define DATA_ADDR_ALIGIN_SIZE 8 64 #define DATA_LEN_ALIGIN_SIZE 64 65 66 /* crypto timeout 500ms, must support more than 32M data per times*/ 67 #define HASH_UPDATE_LIMIT (32 * 1024 * 1024) 68 #define RK_CRYPTO_TIME_OUT 500000 69 70 #define RK_WHILE_TIME_OUT(condition, timeout, ret) { \ 71 u32 time_out = timeout; \ 72 ret = 0; \ 73 while (condition) { \ 74 if (time_out-- == 0) { \ 75 debug("[%s] %d: time out!\n", __func__,\ 76 __LINE__); \ 77 ret = -ETIME; \ 78 break; \ 79 } \ 80 udelay(1); \ 81 } \ 82 } while (0) 83 84 typedef u32 paddr_t; 85 #define virt_to_phys(addr) (((unsigned long)addr) & 0xffffffff) 86 #define phys_to_virt(addr, area) ((unsigned long)addr) 87 88 fdt_addr_t crypto_base; 89 90 static int hw_check_trng_exist(void) 91 { 92 u32 tmp = 0, val = 0; 93 94 tmp = crypto_read(CRYPTO_RNG_SAMPLE_CNT); 95 crypto_write(50, CRYPTO_RNG_SAMPLE_CNT); 96 97 val = crypto_read(CRYPTO_RNG_SAMPLE_CNT); 98 crypto_write(tmp, CRYPTO_RNG_SAMPLE_CNT); 99 100 return val; 101 } 102 103 static void word2byte(u32 word, u8 *ch, u32 endian) 104 { 105 /* 0: Big-Endian 1: Little-Endian */ 106 if (endian == BIG_ENDIAN) { 107 ch[0] = (word >> 24) & 0xff; 108 ch[1] = (word >> 16) & 0xff; 109 ch[2] = (word >> 8) & 0xff; 110 ch[3] = (word >> 0) & 0xff; 111 } else if (endian == LITTLE_ENDIAN) { 112 ch[0] = (word >> 0) & 0xff; 113 ch[1] = (word >> 8) & 0xff; 114 ch[2] = (word >> 16) & 0xff; 115 ch[3] = (word >> 24) & 0xff; 116 } else { 117 ch[0] = 0; 118 ch[1] = 0; 119 ch[2] = 0; 120 ch[3] = 0; 121 } 122 } 123 124 static inline void clear_hash_out_reg(void) 125 { 126 int i; 127 128 /*clear out register*/ 129 for (i = 0; i < 16; i++) 130 crypto_write(0, CRYPTO_HASH_DOUT_0 + 4 * i); 131 } 132 133 static int hw_crypto_reset(void) 134 { 135 u32 tmp = 0, tmp_mask = 0; 136 int ret; 137 138 tmp = CRYPTO_SW_PKA_RESET | CRYPTO_SW_CC_RESET; 139 tmp_mask = tmp << CRYPTO_WRITE_MASK_SHIFT; 140 141 /* reset pka and crypto modules*/ 142 crypto_write(tmp | tmp_mask, CRYPTO_RST_CTL); 143 144 /* wait reset compelete */ 145 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RST_CTL), 146 RK_CRYPTO_TIME_OUT, ret); 147 return ret; 148 } 149 150 static void hw_hash_clean_ctx(struct rk_hash_ctx *ctx) 151 { 152 /* clear hash status */ 153 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 154 155 assert(ctx); 156 assert(ctx->magic == RK_HASH_CTX_MAGIC); 157 158 crypto_hash_cache_free(ctx->hash_cache); 159 160 memset(ctx, 0x00, sizeof(*ctx)); 161 } 162 163 static int rk_hash_init(void *hw_ctx, u32 algo) 164 { 165 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)hw_ctx; 166 u32 reg_ctrl = 0; 167 int ret; 168 169 if (!tmp_ctx) 170 return -EINVAL; 171 172 reg_ctrl = CRYPTO_SW_CC_RESET; 173 crypto_write(reg_ctrl | (reg_ctrl << CRYPTO_WRITE_MASK_SHIFT), 174 CRYPTO_RST_CTL); 175 176 /* wait reset compelete */ 177 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RST_CTL), 178 RK_CRYPTO_TIME_OUT, ret); 179 180 reg_ctrl = 0; 181 tmp_ctx->algo = algo; 182 switch (algo) { 183 case CRYPTO_MD5: 184 reg_ctrl |= CRYPTO_MODE_MD5; 185 tmp_ctx->digest_size = 16; 186 break; 187 case CRYPTO_SHA1: 188 reg_ctrl |= CRYPTO_MODE_SHA1; 189 tmp_ctx->digest_size = 20; 190 break; 191 case CRYPTO_SHA256: 192 reg_ctrl |= CRYPTO_MODE_SHA256; 193 tmp_ctx->digest_size = 32; 194 break; 195 case CRYPTO_SHA512: 196 reg_ctrl |= CRYPTO_MODE_SHA512; 197 tmp_ctx->digest_size = 64; 198 break; 199 200 default: 201 ret = -EINVAL; 202 goto exit; 203 } 204 205 clear_hash_out_reg(); 206 207 /* enable hardware padding */ 208 reg_ctrl |= CRYPTO_HW_PAD_ENABLE; 209 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_HASH_CTL); 210 211 /* FIFO input and output data byte swap */ 212 /* such as B0, B1, B2, B3 -> B3, B2, B1, B0 */ 213 reg_ctrl = CRYPTO_DOUT_BYTESWAP | CRYPTO_DOIN_BYTESWAP; 214 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_FIFO_CTL); 215 216 /* enable src_item_done interrupt */ 217 crypto_write(CRYPTO_SRC_ITEM_INT_EN, CRYPTO_DMA_INT_EN); 218 219 tmp_ctx->magic = RK_HASH_CTX_MAGIC; 220 221 return 0; 222 exit: 223 /* clear hash setting if init failed */ 224 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 225 226 return ret; 227 } 228 229 static int rk_hash_direct_calc(void *hw_data, const u8 *data, 230 u32 data_len, u8 *started_flag, u8 is_last) 231 { 232 struct rockchip_crypto_priv *priv = hw_data; 233 struct rk_hash_ctx *hash_ctx = priv->hw_ctx; 234 struct crypto_lli_desc *lli = &hash_ctx->data_lli; 235 int ret = -EINVAL; 236 u32 tmp = 0; 237 238 assert(IS_ALIGNED((ulong)data, DATA_ADDR_ALIGIN_SIZE)); 239 assert(is_last || IS_ALIGNED(data_len, DATA_LEN_ALIGIN_SIZE)); 240 241 debug("%s: data = %p, len = %u, s = %x, l = %x\n", 242 __func__, data, data_len, *started_flag, is_last); 243 244 memset(lli, 0x00, sizeof(*lli)); 245 lli->src_addr = (u32)virt_to_phys(data); 246 lli->src_len = data_len; 247 lli->dma_ctrl = LLI_DMA_CTRL_SRC_DONE; 248 249 if (is_last) { 250 lli->user_define |= LLI_USER_STRING_LAST; 251 lli->dma_ctrl |= LLI_DMA_CTRL_LAST; 252 } else { 253 lli->next_addr = (u32)virt_to_phys(lli); 254 lli->dma_ctrl |= LLI_DMA_CTRL_PAUSE; 255 } 256 257 if (!(*started_flag)) { 258 lli->user_define |= 259 (LLI_USER_STRING_START | LLI_USER_CPIHER_START); 260 crypto_write((u32)virt_to_phys(lli), CRYPTO_DMA_LLI_ADDR); 261 crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) | 262 CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL); 263 tmp = CRYPTO_DMA_START; 264 *started_flag = 1; 265 } else { 266 tmp = CRYPTO_DMA_RESTART; 267 } 268 269 /* flush cache */ 270 crypto_flush_cacheline((ulong)lli, sizeof(*lli)); 271 crypto_flush_cacheline((ulong)data, data_len); 272 273 /* start calculate */ 274 crypto_write(tmp << CRYPTO_WRITE_MASK_SHIFT | tmp, 275 CRYPTO_DMA_CTL); 276 277 /* wait calc ok */ 278 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_DMA_INT_ST), 279 RK_CRYPTO_TIME_OUT, ret); 280 281 /* clear interrupt status */ 282 tmp = crypto_read(CRYPTO_DMA_INT_ST); 283 crypto_write(tmp, CRYPTO_DMA_INT_ST); 284 285 if (tmp != CRYPTO_SRC_ITEM_DONE_INT_ST && 286 tmp != CRYPTO_ZERO_LEN_INT_ST) { 287 debug("[%s] %d: CRYPTO_DMA_INT_ST = 0x%x\n", 288 __func__, __LINE__, tmp); 289 goto exit; 290 } 291 292 priv->length += data_len; 293 exit: 294 return ret; 295 } 296 297 int rk_hash_update(void *ctx, const u8 *data, u32 data_len) 298 { 299 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 300 int ret = -EINVAL; 301 302 debug("\n"); 303 if (!tmp_ctx || !data) 304 goto exit; 305 306 if (tmp_ctx->digest_size == 0 || tmp_ctx->magic != RK_HASH_CTX_MAGIC) 307 goto exit; 308 309 ret = crypto_hash_update_with_cache(tmp_ctx->hash_cache, 310 data, data_len); 311 312 exit: 313 /* free lli list */ 314 if (ret) 315 hw_hash_clean_ctx(tmp_ctx); 316 317 return ret; 318 } 319 320 int rk_hash_final(void *ctx, u8 *digest, size_t len) 321 { 322 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 323 int ret = -EINVAL; 324 u32 i; 325 326 if (!digest) 327 goto exit; 328 329 if (!tmp_ctx || 330 tmp_ctx->digest_size == 0 || 331 len > tmp_ctx->digest_size || 332 tmp_ctx->magic != RK_HASH_CTX_MAGIC) { 333 goto exit; 334 } 335 336 /* wait hash value ok */ 337 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_HASH_VALID), 338 RK_CRYPTO_TIME_OUT, ret); 339 340 for (i = 0; i < len / 4; i++) 341 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 342 digest + i * 4, BIG_ENDIAN); 343 344 if (len % 4) { 345 u8 tmp_buf[4]; 346 347 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 348 tmp_buf, BIG_ENDIAN); 349 memcpy(digest + i * 4, tmp_buf, len % 4); 350 } 351 352 /* clear hash status */ 353 crypto_write(CRYPTO_HASH_IS_VALID, CRYPTO_HASH_VALID); 354 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 355 356 exit: 357 358 return ret; 359 } 360 361 static int rk_trng(u8 *trng, u32 len) 362 { 363 u32 i, reg_ctrl = 0; 364 int ret = -EINVAL; 365 u32 buf[8]; 366 367 if (len > CRYPTO_TRNG_MAX) 368 return -EINVAL; 369 370 memset(buf, 0, sizeof(buf)); 371 372 /* enable osc_ring to get entropy, sample period is set as 50 */ 373 crypto_write(50, CRYPTO_RNG_SAMPLE_CNT); 374 375 reg_ctrl |= CRYPTO_RNG_256_bit_len; 376 reg_ctrl |= CRYPTO_RNG_SLOWER_SOC_RING_1; 377 reg_ctrl |= CRYPTO_RNG_ENABLE; 378 reg_ctrl |= CRYPTO_RNG_START; 379 reg_ctrl |= CRYPTO_WRITE_MASK_ALL; 380 381 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_RNG_CTL); 382 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RNG_CTL) & CRYPTO_RNG_START, 383 RK_CRYPTO_TIME_OUT, ret); 384 385 if (ret == 0) { 386 for (i = 0; i < ARRAY_SIZE(buf); i++) 387 buf[i] = crypto_read(CRYPTO_RNG_DOUT_0 + i * 4); 388 memcpy(trng, buf, len); 389 } 390 391 /* close TRNG */ 392 crypto_write(0 | CRYPTO_WRITE_MASK_ALL, CRYPTO_RNG_CTL); 393 394 return ret; 395 } 396 397 static u32 rockchip_crypto_capability(struct udevice *dev) 398 { 399 u32 val = 0; 400 401 val = CRYPTO_MD5 | 402 CRYPTO_SHA1 | 403 CRYPTO_SHA256 | 404 #if !defined(CONFIG_ROCKCHIP_RK1808) 405 CRYPTO_SHA512 | 406 #endif 407 CRYPTO_RSA512 | 408 CRYPTO_RSA1024 | 409 CRYPTO_RSA2048 | 410 CRYPTO_RSA3072 | 411 CRYPTO_RSA4096; 412 413 if (hw_check_trng_exist()) 414 val |= CRYPTO_TRNG; 415 416 return val; 417 } 418 419 static int rockchip_crypto_sha_init(struct udevice *dev, sha_context *ctx) 420 { 421 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 422 struct rk_hash_ctx *hash_ctx = priv->hw_ctx; 423 424 if (!ctx) 425 return -EINVAL; 426 427 memset(hash_ctx, 0x00, sizeof(*hash_ctx)); 428 429 priv->length = 0; 430 431 hash_ctx->hash_cache = crypto_hash_cache_alloc(rk_hash_direct_calc, 432 priv, ctx->length, 433 DATA_ADDR_ALIGIN_SIZE, 434 DATA_LEN_ALIGIN_SIZE); 435 if (!hash_ctx->hash_cache) 436 return -EFAULT; 437 438 return rk_hash_init(hash_ctx, ctx->algo); 439 } 440 441 static int rockchip_crypto_sha_update(struct udevice *dev, 442 u32 *input, u32 len) 443 { 444 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 445 int ret, i; 446 u8 *p; 447 448 if (!len) 449 return -EINVAL; 450 451 p = (u8 *)input; 452 453 for (i = 0; i < len / HASH_UPDATE_LIMIT; i++, p += HASH_UPDATE_LIMIT) { 454 ret = rk_hash_update(priv->hw_ctx, p, HASH_UPDATE_LIMIT); 455 if (ret) 456 goto exit; 457 } 458 459 if (len % HASH_UPDATE_LIMIT) 460 ret = rk_hash_update(priv->hw_ctx, p, len % HASH_UPDATE_LIMIT); 461 462 exit: 463 return ret; 464 } 465 466 static int rockchip_crypto_sha_final(struct udevice *dev, 467 sha_context *ctx, u8 *output) 468 { 469 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 470 u32 nbits; 471 int ret; 472 473 nbits = crypto_algo_nbits(ctx->algo); 474 475 if (priv->length != ctx->length) { 476 printf("total length(0x%08x) != init length(0x%08x)!\n", 477 priv->length, ctx->length); 478 ret = -EIO; 479 goto exit; 480 } 481 482 ret = rk_hash_final(priv->hw_ctx, (u8 *)output, BITS2BYTE(nbits)); 483 484 exit: 485 hw_hash_clean_ctx(priv->hw_ctx); 486 return ret; 487 } 488 489 #if CONFIG_IS_ENABLED(ROCKCHIP_RSA) 490 static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, 491 u8 *sign, u8 *output) 492 { 493 struct mpa_num *mpa_m = NULL, *mpa_e = NULL, *mpa_n = NULL; 494 struct mpa_num *mpa_c = NULL, *mpa_result = NULL; 495 u32 n_bits, n_words; 496 u32 *rsa_result; 497 int ret; 498 499 if (!ctx) 500 return -EINVAL; 501 502 if (ctx->algo != CRYPTO_RSA512 && 503 ctx->algo != CRYPTO_RSA1024 && 504 ctx->algo != CRYPTO_RSA2048 && 505 ctx->algo != CRYPTO_RSA3072 && 506 ctx->algo != CRYPTO_RSA4096) 507 return -EINVAL; 508 509 n_bits = crypto_algo_nbits(ctx->algo); 510 n_words = BITS2WORD(n_bits); 511 512 rsa_result = malloc(BITS2BYTE(n_bits)); 513 if (!rsa_result) 514 return -ENOMEM; 515 516 memset(rsa_result, 0x00, BITS2BYTE(n_bits)); 517 518 ret = rk_mpa_alloc(&mpa_m); 519 ret |= rk_mpa_alloc(&mpa_e); 520 ret |= rk_mpa_alloc(&mpa_n); 521 ret |= rk_mpa_alloc(&mpa_c); 522 ret |= rk_mpa_alloc(&mpa_result); 523 if (ret) 524 goto exit; 525 526 mpa_m->d = (void *)sign; 527 mpa_e->d = (void *)ctx->e; 528 mpa_n->d = (void *)ctx->n; 529 mpa_c->d = (void *)ctx->c; 530 mpa_result->d = (void *)rsa_result; 531 532 mpa_m->size = n_words; 533 mpa_e->size = n_words; 534 mpa_n->size = n_words; 535 mpa_c->size = n_words; 536 mpa_result->size = n_words; 537 538 ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result); 539 if (!ret) 540 memcpy(output, rsa_result, BITS2BYTE(n_bits)); 541 542 exit: 543 free(rsa_result); 544 rk_mpa_free(&mpa_m); 545 rk_mpa_free(&mpa_e); 546 rk_mpa_free(&mpa_n); 547 rk_mpa_free(&mpa_c); 548 rk_mpa_free(&mpa_result); 549 550 return ret; 551 } 552 #else 553 static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, 554 u8 *sign, u8 *output) 555 { 556 return -ENOSYS; 557 } 558 #endif 559 560 static int rockchip_crypto_get_trng(struct udevice *dev, u8 *output, u32 len) 561 { 562 int ret; 563 u32 i; 564 565 if (!dev || !output || !len) 566 return -EINVAL; 567 568 for (i = 0; i < len / CRYPTO_TRNG_MAX; i++) { 569 ret = rk_trng(output + i * CRYPTO_TRNG_MAX, CRYPTO_TRNG_MAX); 570 if (ret) 571 goto fail; 572 } 573 574 ret = rk_trng(output + i * CRYPTO_TRNG_MAX, len % CRYPTO_TRNG_MAX); 575 576 fail: 577 return ret; 578 } 579 580 static const struct dm_crypto_ops rockchip_crypto_ops = { 581 .capability = rockchip_crypto_capability, 582 .sha_init = rockchip_crypto_sha_init, 583 .sha_update = rockchip_crypto_sha_update, 584 .sha_final = rockchip_crypto_sha_final, 585 .rsa_verify = rockchip_crypto_rsa_verify, 586 .get_trng = rockchip_crypto_get_trng, 587 }; 588 589 /* 590 * Only use "clocks" to parse crypto clock id and use rockchip_get_clk(). 591 * Because we always add crypto node in U-Boot dts, when kernel dtb enabled : 592 * 593 * 1. There is cru phandle mismatch between U-Boot and kernel dtb; 594 * 2. CONFIG_OF_SPL_REMOVE_PROPS removes clock property; 595 */ 596 static int rockchip_crypto_ofdata_to_platdata(struct udevice *dev) 597 { 598 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 599 int len, ret = -EINVAL; 600 601 if (!dev_read_prop(dev, "clocks", &len)) { 602 printf("Can't find \"clocks\" property\n"); 603 return -EINVAL; 604 } 605 606 memset(priv, 0x00, sizeof(*priv)); 607 priv->clocks = malloc(len); 608 if (!priv->clocks) 609 return -ENOMEM; 610 611 priv->nclocks = len / sizeof(u32); 612 if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks, 613 priv->nclocks)) { 614 printf("Can't read \"clocks\" property\n"); 615 ret = -EINVAL; 616 goto exit; 617 } 618 619 if (!dev_read_prop(dev, "clock-frequency", &len)) { 620 printf("Can't find \"clock-frequency\" property\n"); 621 ret = -EINVAL; 622 goto exit; 623 } 624 625 priv->frequencies = malloc(len); 626 if (!priv->frequencies) { 627 ret = -ENOMEM; 628 goto exit; 629 } 630 631 priv->nclocks = len / sizeof(u32); 632 if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies, 633 priv->nclocks)) { 634 printf("Can't read \"clock-frequency\" property\n"); 635 ret = -EINVAL; 636 goto exit; 637 } 638 639 priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev); 640 641 crypto_base = priv->reg; 642 643 return 0; 644 exit: 645 if (priv->clocks) 646 free(priv->clocks); 647 648 if (priv->frequencies) 649 free(priv->frequencies); 650 651 return ret; 652 } 653 654 static int rockchip_crypto_probe(struct udevice *dev) 655 { 656 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 657 int i, ret = 0; 658 u32* clocks; 659 660 priv->hw_ctx = memalign(LLI_ADDR_ALIGIN_SIZE, 661 sizeof(struct rk_hash_ctx)); 662 if (!priv->hw_ctx) 663 return -ENOMEM; 664 665 ret = rockchip_get_clk(&priv->clk.dev); 666 if (ret) { 667 printf("Failed to get clk device, ret=%d\n", ret); 668 return ret; 669 } 670 671 clocks = (u32 *)priv->clocks; 672 for (i = 0; i < priv->nclocks; i++) { 673 priv->clk.id = clocks[i * 2 + 1]; 674 ret = clk_set_rate(&priv->clk, priv->frequencies[i]); 675 if (ret < 0) { 676 printf("%s: Failed to set clk(%ld): ret=%d\n", 677 __func__, priv->clk.id, ret); 678 return ret; 679 } 680 } 681 682 hw_crypto_reset(); 683 684 return 0; 685 } 686 687 static const struct udevice_id rockchip_crypto_ids[] = { 688 { .compatible = "rockchip,px30-crypto" }, 689 { .compatible = "rockchip,rk1808-crypto" }, 690 { .compatible = "rockchip,rk3308-crypto" }, 691 { .compatible = "rockchip,rv1126-crypto" }, 692 { .compatible = "rockchip,rk3568-crypto" }, 693 { } 694 }; 695 696 U_BOOT_DRIVER(rockchip_crypto_v2) = { 697 .name = "rockchip_crypto_v2", 698 .id = UCLASS_CRYPTO, 699 .of_match = rockchip_crypto_ids, 700 .ops = &rockchip_crypto_ops, 701 .probe = rockchip_crypto_probe, 702 .ofdata_to_platdata = rockchip_crypto_ofdata_to_platdata, 703 .priv_auto_alloc_size = sizeof(struct rockchip_crypto_priv), 704 }; 705