1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <clk.h> 8 #include <crypto.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/clock.h> 13 #include <rockchip/crypto_v2.h> 14 #include <rockchip/crypto_v2_pka.h> 15 16 struct rockchip_crypto_priv { 17 fdt_addr_t reg; 18 struct clk clk; 19 u32 frequency; 20 char *clocks; 21 u32 *frequencies; 22 u32 nclocks; 23 u32 length; 24 void *hw_ctx; 25 }; 26 27 #define LLI_ADDR_ALIGIN_SIZE 8 28 #define DATA_ADDR_ALIGIN_SIZE 8 29 #define RK_CRYPTO_TIME_OUT 50000 /* max 50ms */ 30 31 #define RK_WHILE_TIME_OUT(condition, timeout, ret) { \ 32 u32 time_out = timeout; \ 33 while (condition) { \ 34 if (time_out-- == 0) { \ 35 printf("[%s] %d: time out!", __func__, \ 36 __LINE__); \ 37 ret = -ETIME; \ 38 break; \ 39 } \ 40 udelay(1); \ 41 } \ 42 ret = 0; \ 43 } while (0) 44 45 typedef u32 paddr_t; 46 #define virt_to_phys(addr) (((unsigned long)addr) & 0xffffffff) 47 #define phys_to_virt(addr, area) ((unsigned long)addr) 48 49 static const u8 null_hash_sha1_value[] = { 50 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 51 0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90, 52 0xaf, 0xd8, 0x07, 0x09 53 }; 54 55 static const u8 null_hash_md5_value[] = { 56 0xd4, 0x1d, 0x8c, 0xd9, 0x8f, 0x00, 0xb2, 0x04, 57 0xe9, 0x80, 0x09, 0x98, 0xec, 0xf8, 0x42, 0x7e 58 }; 59 60 static const u8 null_hash_sha256_value[] = { 61 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 62 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24, 63 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c, 64 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55 65 }; 66 67 fdt_addr_t crypto_base; 68 69 static void word2byte(u32 word, u8 *ch, u32 endian) 70 { 71 /* 0: Big-Endian 1: Little-Endian */ 72 if (endian == BIG_ENDIAN) { 73 ch[0] = (word >> 24) & 0xff; 74 ch[1] = (word >> 16) & 0xff; 75 ch[2] = (word >> 8) & 0xff; 76 ch[3] = (word >> 0) & 0xff; 77 } else if (endian == LITTLE_ENDIAN) { 78 ch[0] = (word >> 0) & 0xff; 79 ch[1] = (word >> 8) & 0xff; 80 ch[2] = (word >> 16) & 0xff; 81 ch[3] = (word >> 24) & 0xff; 82 } else { 83 ch[0] = 0; 84 ch[1] = 0; 85 ch[2] = 0; 86 ch[3] = 0; 87 } 88 } 89 90 static inline void clear_hash_out_reg(void) 91 { 92 int i; 93 94 /*clear out register*/ 95 for (i = 0; i < 16; i++) 96 crypto_write(0, CRYPTO_HASH_DOUT_0 + 4 * i); 97 } 98 99 static int hw_crypto_reset(void) 100 { 101 u32 tmp = 0, tmp_mask = 0; 102 int ret; 103 104 tmp = CRYPTO_SW_PKA_RESET | CRYPTO_SW_CC_RESET; 105 tmp_mask = tmp << CRYPTO_WRITE_MASK_SHIFT; 106 107 /* reset pka and crypto modules*/ 108 crypto_write(tmp | tmp_mask, CRYPTO_RST_CTL); 109 110 /* wait reset compelete */ 111 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RST_CTL), 112 RK_CRYPTO_TIME_OUT, ret); 113 return ret; 114 } 115 116 static void hw_hash_common_clean_ctx(struct rk_hash_ctx *ctx) 117 { 118 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 119 120 if (ctx->free_data_lli) 121 free(ctx->free_data_lli); 122 123 if (ctx->cur_data_lli) 124 free(ctx->cur_data_lli); 125 126 if (ctx->vir_src_addr) 127 free(ctx->vir_src_addr); 128 memset(ctx, 0x00, sizeof(*ctx)); 129 } 130 131 static void hw_hash_clean_ctx(struct rk_hash_ctx *ctx) 132 { 133 /* clear hash status */ 134 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 135 136 /* free tmp buff */ 137 if (ctx && ctx->magic == RK_HASH_CTX_MAGIC) 138 hw_hash_common_clean_ctx(ctx); 139 } 140 141 int rk_hash_init(void *hw_ctx, u32 algo) 142 { 143 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)hw_ctx; 144 u32 reg_ctrl = 0; 145 int ret; 146 147 if (!tmp_ctx) 148 return -EINVAL; 149 150 memset(tmp_ctx, 0x00, sizeof(*tmp_ctx)); 151 152 tmp_ctx->algo = algo; 153 switch (algo) { 154 case CRYPTO_MD5: 155 reg_ctrl |= CRYPTO_MODE_MD5; 156 tmp_ctx->digest_size = 16; 157 tmp_ctx->null_hash = null_hash_md5_value; 158 break; 159 case CRYPTO_SHA1: 160 reg_ctrl |= CRYPTO_MODE_SHA1; 161 tmp_ctx->digest_size = 20; 162 tmp_ctx->null_hash = null_hash_sha1_value; 163 break; 164 case CRYPTO_SHA256: 165 reg_ctrl |= CRYPTO_MODE_SHA256; 166 tmp_ctx->digest_size = 32; 167 tmp_ctx->null_hash = null_hash_sha256_value; 168 break; 169 default: 170 ret = -EINVAL; 171 goto exit; 172 } 173 174 clear_hash_out_reg(); 175 176 /* enable hardware padding */ 177 reg_ctrl |= CRYPTO_HW_PAD_ENABLE; 178 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_HASH_CTL); 179 180 /* FIFO input and output data byte swap */ 181 /* such as B0, B1, B2, B3 -> B3, B2, B1, B0 */ 182 reg_ctrl = CRYPTO_DOUT_BYTESWAP | CRYPTO_DOIN_BYTESWAP; 183 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_FIFO_CTL); 184 185 /* disable all interrupt */ 186 crypto_write(0x0, CRYPTO_DMA_INT_EN); 187 188 tmp_ctx->magic = RK_HASH_CTX_MAGIC; 189 190 return 0; 191 exit: 192 /* clear hash setting if init failed */ 193 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 194 195 return ret; 196 } 197 198 int rk_hash_update(void *ctx, const u8 *data, u32 data_len) 199 { 200 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 201 struct crypto_lli_desc *free_lli_desp = NULL; 202 struct crypto_lli_desc *lli_desp = NULL; 203 u32 tmp, temp_data_len = 0; 204 u8 *vir_src_addr = NULL; 205 int ret = -EINVAL; 206 207 if (!tmp_ctx || !data) 208 goto error; 209 210 if (tmp_ctx->digest_size == 0 || tmp_ctx->magic != RK_HASH_CTX_MAGIC) 211 goto error; 212 213 /* update will keep cache one calculate request in memmory */ 214 /* because last calculate request should calculate in final */ 215 if (!tmp_ctx->cur_data_lli) { 216 lli_desp = (struct crypto_lli_desc *) 217 memalign(DATA_ADDR_ALIGIN_SIZE, 218 sizeof(struct crypto_lli_desc)); 219 if (!lli_desp) 220 goto error; 221 222 free_lli_desp = (struct crypto_lli_desc *) 223 memalign(DATA_ADDR_ALIGIN_SIZE, 224 sizeof(struct crypto_lli_desc)); 225 if (!free_lli_desp) { 226 free(lli_desp); 227 goto error; 228 } 229 230 memset(lli_desp, 0x00, sizeof(*lli_desp)); 231 vir_src_addr = (u8 *)memalign(DATA_ADDR_ALIGIN_SIZE, 232 HASH_MAX_SIZE); 233 if (!vir_src_addr) { 234 free(lli_desp); 235 free(free_lli_desp); 236 printf("[%s] %d: memalign fail!", __func__, __LINE__); 237 goto error; 238 } 239 240 lli_desp->src_addr = (u32)virt_to_phys(vir_src_addr); 241 lli_desp->user_define = LLI_USER_CPIHER_START | 242 LLI_USER_STRING_START; 243 tmp_ctx->cur_data_lli = lli_desp; 244 tmp_ctx->free_data_lli = free_lli_desp; 245 tmp_ctx->vir_src_addr = vir_src_addr; 246 247 /* write first lli dma address to reg */ 248 crypto_write((u32)virt_to_phys(tmp_ctx->cur_data_lli), 249 CRYPTO_DMA_LLI_ADDR); 250 } 251 252 ret = 0; 253 while (data_len) { 254 lli_desp = (struct crypto_lli_desc *)tmp_ctx->cur_data_lli; 255 vir_src_addr = (u8 *)phys_to_virt((paddr_t)lli_desp->src_addr, 256 MEM_AREA_TEE_RAM); 257 if (data_len + lli_desp->src_len > HASH_MAX_SIZE) { 258 temp_data_len = HASH_MAX_SIZE - lli_desp->src_len; 259 memcpy(vir_src_addr + lli_desp->src_len, data, 260 temp_data_len); 261 data_len -= temp_data_len; 262 data += temp_data_len; 263 264 free_lli_desp = tmp_ctx->free_data_lli; 265 266 memset(free_lli_desp, 0x00, sizeof(*free_lli_desp)); 267 lli_desp->src_len = HASH_MAX_SIZE; 268 lli_desp->next_addr = (u32)virt_to_phys(free_lli_desp); 269 /* item done and pause */ 270 lli_desp->dma_ctrl = LLI_DMA_CTRL_PAUSE | 271 LLI_DMA_CTRL_SRC_DONE; 272 273 if (tmp_ctx->dma_started == 0) { 274 /* start calculate */ 275 crypto_write((CRYPTO_HASH_ENABLE << 276 CRYPTO_WRITE_MASK_SHIFT) | 277 CRYPTO_HASH_ENABLE, 278 CRYPTO_HASH_CTL); 279 tmp = CRYPTO_DMA_START; 280 tmp_ctx->dma_started = 1; 281 } else { 282 /* restart calculate */ 283 tmp = CRYPTO_DMA_RESTART; 284 } 285 286 /* flush cache */ 287 cache_op_inner(DCACHE_AREA_CLEAN, lli_desp, 288 sizeof(*lli_desp)); 289 cache_op_inner(DCACHE_AREA_CLEAN, vir_src_addr, 290 lli_desp->src_len); 291 292 /* start calculate */ 293 crypto_write(tmp << CRYPTO_WRITE_MASK_SHIFT | tmp, 294 CRYPTO_DMA_CTL); 295 296 /* wait calc ok */ 297 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_DMA_INT_ST), 298 RK_CRYPTO_TIME_OUT, ret); 299 300 /* clear interrupt status */ 301 tmp = crypto_read(CRYPTO_DMA_INT_ST); 302 crypto_write(tmp, CRYPTO_DMA_INT_ST); 303 304 if (tmp != CRYPTO_SRC_ITEM_DONE_INT_ST && 305 tmp != CRYPTO_ZERO_LEN_INT_ST) { 306 printf("[%s] %d: CRYPTO_DMA_INT_ST = 0x%x", 307 __func__, __LINE__, tmp); 308 goto error; 309 } 310 311 /* after calc one block, swap free lli and cur lli */ 312 free_lli_desp->src_addr = lli_desp->src_addr; 313 tmp_ctx->free_data_lli = tmp_ctx->cur_data_lli; 314 tmp_ctx->cur_data_lli = free_lli_desp; 315 free_lli_desp = NULL; 316 } else { 317 /* cache first calculate request to buff */ 318 memcpy(vir_src_addr + lli_desp->src_len, 319 data, data_len); 320 lli_desp->src_len += data_len; 321 data_len = 0; 322 } 323 } 324 325 return ret; 326 327 error: 328 /* free lli list */ 329 hw_hash_clean_ctx(tmp_ctx); 330 331 return ret; 332 } 333 334 int rk_hash_final(void *ctx, u8 *digest, size_t len) 335 { 336 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 337 struct crypto_lli_desc *lli_desp = NULL; 338 int ret = -EINVAL; 339 u32 i, tmp; 340 341 if (!digest) 342 goto exit; 343 344 if (!tmp_ctx || 345 !tmp_ctx->cur_data_lli || 346 tmp_ctx->digest_size == 0 || 347 len > tmp_ctx->digest_size || 348 tmp_ctx->magic != RK_HASH_CTX_MAGIC) { 349 goto exit; 350 } 351 352 /* to find the last block */ 353 lli_desp = (struct crypto_lli_desc *)tmp_ctx->cur_data_lli; 354 if (lli_desp->next_addr != 0) 355 goto exit; 356 357 /* if data len is zero, return null hash value immediately*/ 358 if (tmp_ctx->dma_started == 0 && 359 lli_desp->src_len == 0 && 360 !tmp_ctx->null_hash) { 361 memcpy(digest, tmp_ctx->null_hash, len); 362 ret = 0; 363 goto exit; 364 } 365 366 /* set LLI_USER_STRING_LAST to tell crypto this block is last one */ 367 lli_desp->user_define |= LLI_USER_STRING_LAST; 368 lli_desp->dma_ctrl = LLI_DMA_CTRL_LIST_DONE | LLI_DMA_CTRL_LAST; 369 cache_op_inner(DCACHE_AREA_CLEAN, lli_desp, sizeof(*lli_desp)); 370 cache_op_inner(DCACHE_AREA_CLEAN, tmp_ctx->vir_src_addr, 371 lli_desp->src_len); 372 373 if (tmp_ctx->dma_started == 0) { 374 crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) | 375 CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL); 376 crypto_write((CRYPTO_DMA_START << CRYPTO_WRITE_MASK_SHIFT) | 377 CRYPTO_DMA_START, CRYPTO_DMA_CTL); 378 } else { 379 crypto_write((CRYPTO_DMA_RESTART << CRYPTO_WRITE_MASK_SHIFT) | 380 CRYPTO_DMA_RESTART, CRYPTO_DMA_CTL); 381 tmp_ctx->dma_started = 1; 382 } 383 384 /* wait dma trans ok */ 385 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_DMA_INT_ST), 386 RK_CRYPTO_TIME_OUT, ret); 387 388 /* clear interrupt status */ 389 tmp = crypto_read(CRYPTO_DMA_INT_ST); 390 crypto_write(tmp, CRYPTO_DMA_INT_ST); 391 392 if (tmp != CRYPTO_LIST_DONE_INT_ST) { 393 ret = -EIO; 394 goto exit; 395 } 396 397 /* wait hash value ok */ 398 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_HASH_VALID), 399 RK_CRYPTO_TIME_OUT, ret); 400 401 for (i = 0; i < len / 4; i++) 402 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 403 digest + i * 4, BIG_ENDIAN); 404 405 if (len % 4) { 406 u8 tmp_buf[4]; 407 408 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 409 tmp_buf, BIG_ENDIAN); 410 memcpy(digest + i * 4, tmp_buf, len % 4); 411 } 412 413 /* clear hash status */ 414 crypto_write(CRYPTO_HASH_IS_VALID, CRYPTO_HASH_VALID); 415 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 416 417 exit: 418 /* free lli list */ 419 hw_hash_clean_ctx(tmp_ctx); 420 421 return ret; 422 } 423 424 static u32 rockchip_crypto_capability(struct udevice *dev) 425 { 426 return CRYPTO_MD5 | 427 CRYPTO_SHA1 | 428 CRYPTO_SHA256 | 429 CRYPTO_RSA512 | 430 CRYPTO_RSA1024 | 431 CRYPTO_RSA2048 | 432 CRYPTO_RSA3072 | 433 CRYPTO_RSA4096; 434 } 435 436 static int rockchip_crypto_sha_init(struct udevice *dev, sha_context *ctx) 437 { 438 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 439 440 if (!ctx) 441 return -EINVAL; 442 443 priv->hw_ctx = malloc(sizeof(struct rk_hash_ctx)); 444 if (!priv->hw_ctx) 445 return -ENOMEM; 446 447 memset(priv->hw_ctx, 0x00, sizeof(struct rk_hash_ctx)); 448 449 return rk_hash_init(priv->hw_ctx, ctx->algo); 450 } 451 452 static int rockchip_crypto_sha_update(struct udevice *dev, 453 u32 *input, u32 len) 454 { 455 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 456 457 if (!len) 458 return -EINVAL; 459 460 return rk_hash_update(priv->hw_ctx, (u8 *)input, len); 461 } 462 463 static int rockchip_crypto_sha_final(struct udevice *dev, 464 sha_context *ctx, u8 *output) 465 { 466 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 467 u32 nbits; 468 int ret; 469 470 nbits = crypto_algo_nbits(ctx->algo); 471 472 ret = rk_hash_final(priv->hw_ctx, (u8 *)output, BITS2BYTE(nbits)); 473 if (priv->hw_ctx) { 474 free(priv->hw_ctx); 475 priv->hw_ctx = 0; 476 } 477 478 return ret; 479 } 480 481 static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, 482 u8 *sign, u8 *output) 483 { 484 struct mpa_num *mpa_m = NULL, *mpa_e = NULL, *mpa_n = NULL; 485 struct mpa_num *mpa_c = NULL, *mpa_result = NULL; 486 u32 n_bits, n_words; 487 u32 *rsa_result; 488 int ret; 489 490 if (!ctx) 491 return -EINVAL; 492 493 if (ctx->algo != CRYPTO_RSA512 && 494 ctx->algo != CRYPTO_RSA1024 && 495 ctx->algo != CRYPTO_RSA2048 && 496 ctx->algo != CRYPTO_RSA3072 && 497 ctx->algo != CRYPTO_RSA4096) 498 return -EINVAL; 499 500 n_bits = crypto_algo_nbits(ctx->algo); 501 n_words = BITS2WORD(n_bits); 502 503 rsa_result = malloc(BITS2BYTE(n_bits)); 504 if (!rsa_result) 505 return -ENOMEM; 506 507 memset(rsa_result, 0x00, BITS2BYTE(n_bits)); 508 509 ret = rk_mpa_alloc(&mpa_m); 510 ret |= rk_mpa_alloc(&mpa_e); 511 ret |= rk_mpa_alloc(&mpa_n); 512 ret |= rk_mpa_alloc(&mpa_c); 513 ret |= rk_mpa_alloc(&mpa_result); 514 if (ret) 515 goto exit; 516 517 mpa_m->d = (void *)sign; 518 mpa_e->d = (void *)ctx->e; 519 mpa_n->d = (void *)ctx->n; 520 mpa_c->d = (void *)ctx->c; 521 mpa_result->d = (void *)rsa_result; 522 523 mpa_m->size = n_words; 524 mpa_e->size = n_words; 525 mpa_n->size = n_words; 526 mpa_c->size = n_words; 527 mpa_result->size = n_words; 528 529 ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result); 530 if (!ret) 531 memcpy(output, rsa_result, BITS2BYTE(n_bits)); 532 533 exit: 534 free(rsa_result); 535 rk_mpa_free(&mpa_m); 536 rk_mpa_free(&mpa_e); 537 rk_mpa_free(&mpa_n); 538 rk_mpa_free(&mpa_c); 539 rk_mpa_free(&mpa_result); 540 541 return ret; 542 } 543 544 static const struct dm_crypto_ops rockchip_crypto_ops = { 545 .capability = rockchip_crypto_capability, 546 .sha_init = rockchip_crypto_sha_init, 547 .sha_update = rockchip_crypto_sha_update, 548 .sha_final = rockchip_crypto_sha_final, 549 .rsa_verify = rockchip_crypto_rsa_verify, 550 }; 551 552 /* 553 * Only use "clocks" to parse crypto clock id and use rockchip_get_clk(). 554 * Because we always add crypto node in U-Boot dts, when kernel dtb enabled : 555 * 556 * 1. There is cru phandle mismatch between U-Boot and kernel dtb; 557 * 2. CONFIG_OF_SPL_REMOVE_PROPS removes clock property; 558 */ 559 static int rockchip_crypto_ofdata_to_platdata(struct udevice *dev) 560 { 561 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 562 int len, ret = -EINVAL; 563 564 if (!dev_read_prop(dev, "clocks", &len)) { 565 printf("Can't find \"clocks\" property\n"); 566 return -EINVAL; 567 } 568 569 memset(priv, 0x00, sizeof(*priv)); 570 priv->clocks = malloc(len); 571 if (!priv->clocks) 572 return -ENOMEM; 573 574 priv->nclocks = len / sizeof(u32); 575 if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks, 576 priv->nclocks)) { 577 printf("Can't read \"clocks\" property\n"); 578 ret = -EINVAL; 579 goto exit; 580 } 581 582 if (!dev_read_prop(dev, "clock-frequency", &len)) { 583 printf("Can't find \"clock-frequency\" property\n"); 584 ret = -EINVAL; 585 goto exit; 586 } 587 588 priv->frequencies = malloc(len); 589 if (!priv->frequencies) { 590 ret = -ENOMEM; 591 goto exit; 592 } 593 594 priv->nclocks = len / sizeof(u32); 595 if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies, 596 priv->nclocks)) { 597 printf("Can't read \"clock-frequency\" property\n"); 598 ret = -EINVAL; 599 goto exit; 600 } 601 602 priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev); 603 604 crypto_base = priv->reg; 605 606 return 0; 607 exit: 608 if (priv->clocks) 609 free(priv->clocks); 610 611 if (priv->frequencies) 612 free(priv->frequencies); 613 614 return ret; 615 } 616 617 static int rockchip_crypto_probe(struct udevice *dev) 618 { 619 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 620 int i, ret = 0; 621 u32* clocks; 622 623 ret = rockchip_get_clk(&priv->clk.dev); 624 if (ret) { 625 printf("Failed to get clk device, ret=%d\n", ret); 626 return ret; 627 } 628 629 clocks = (u32 *)priv->clocks; 630 for (i = 0; i < priv->nclocks; i++) { 631 priv->clk.id = clocks[i * 2 + 1]; 632 ret = clk_set_rate(&priv->clk, priv->frequencies[i]); 633 if (ret < 0) { 634 printf("%s: Failed to set clk(%ld): ret=%d\n", 635 __func__, priv->clk.id, ret); 636 return ret; 637 } 638 } 639 640 hw_crypto_reset(); 641 642 return 0; 643 } 644 645 static const struct udevice_id rockchip_crypto_ids[] = { 646 { .compatible = "rockchip,px30-crypto" }, 647 { } 648 }; 649 650 U_BOOT_DRIVER(rockchip_crypto_v2) = { 651 .name = "rockchip_crypto_v2", 652 .id = UCLASS_CRYPTO, 653 .of_match = rockchip_crypto_ids, 654 .ops = &rockchip_crypto_ops, 655 .probe = rockchip_crypto_probe, 656 .ofdata_to_platdata = rockchip_crypto_ofdata_to_platdata, 657 .priv_auto_alloc_size = sizeof(struct rockchip_crypto_priv), 658 }; 659