1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <clk.h> 8 #include <crypto.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <clk-uclass.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/arch/clock.h> 14 #include <rockchip/crypto_ecc.h> 15 #include <rockchip/crypto_hash_cache.h> 16 #include <rockchip/crypto_v2.h> 17 #include <rockchip/crypto_v2_pka.h> 18 19 #define RK_HASH_CTX_MAGIC 0x1A1A1A1A 20 21 #define CRYPTO_MAJOR_VER(ver) ((ver) & 0x0f000000) 22 23 #define CRYPTO_MAJOR_VER_3 0x03000000 24 #define CRYPTO_MAJOR_VER_4 0x04000000 25 26 #ifdef DEBUG 27 #define IMSG(format, ...) printf("[%s, %05d]-trace: " format "\n", \ 28 __func__, __LINE__, ##__VA_ARGS__) 29 #else 30 #define IMSG(format, ...) 31 #endif 32 33 struct crypto_lli_desc { 34 u32 src_addr; 35 u32 src_len; 36 u32 dst_addr; 37 u32 dst_len; 38 u32 user_define; 39 u32 reserve; 40 u32 dma_ctrl; 41 u32 next_addr; 42 }; 43 44 struct rk_hash_ctx { 45 struct crypto_lli_desc data_lli; /* lli desc */ 46 struct crypto_hash_cache *hash_cache; 47 u32 magic; /* to check ctx */ 48 u32 algo; /* hash algo */ 49 u8 digest_size; /* hash out length */ 50 u8 reserved[3]; 51 }; 52 53 struct rk_crypto_soc_data { 54 u32 capability; 55 u32 (*dynamic_cap)(void); 56 }; 57 58 struct rockchip_crypto_priv { 59 fdt_addr_t reg; 60 u32 frequency; 61 char *clocks; 62 u32 *frequencies; 63 u32 nclocks; 64 u32 freq_nclocks; 65 u32 length; 66 struct rk_hash_ctx *hw_ctx; 67 struct rk_crypto_soc_data *soc_data; 68 }; 69 70 #define LLI_ADDR_ALIGN_SIZE 8 71 #define DATA_ADDR_ALIGN_SIZE 8 72 #define DATA_LEN_ALIGN_SIZE 64 73 74 /* crypto timeout 500ms, must support more than 32M data per times*/ 75 #define HASH_UPDATE_LIMIT (32 * 1024 * 1024) 76 #define RK_CRYPTO_TIMEOUT 500000 77 78 #define RK_POLL_TIMEOUT(condition, timeout) \ 79 ({ \ 80 int time_out = timeout; \ 81 while (condition) { \ 82 if (--time_out <= 0) { \ 83 debug("[%s] %d: time out!\n", __func__,\ 84 __LINE__); \ 85 break; \ 86 } \ 87 udelay(1); \ 88 } \ 89 (time_out <= 0) ? -ETIMEDOUT : 0; \ 90 }) 91 92 #define WAIT_TAG_VALID(channel, timeout) ({ \ 93 u32 tag_mask = CRYPTO_CH0_TAG_VALID << (channel);\ 94 int ret = 0;\ 95 if (is_check_tag_valid()) { \ 96 ret = RK_POLL_TIMEOUT(!(crypto_read(CRYPTO_TAG_VALID) & tag_mask),\ 97 timeout);\ 98 } \ 99 crypto_write(crypto_read(CRYPTO_TAG_VALID) & tag_mask, CRYPTO_TAG_VALID);\ 100 ret;\ 101 }) 102 103 #define virt_to_phys(addr) (((unsigned long)addr) & 0xffffffff) 104 #define phys_to_virt(addr, area) ((unsigned long)addr) 105 106 #define align_malloc(bytes, alignment) memalign(alignment, bytes) 107 #define align_free(addr) do {if (addr) free(addr);} while (0) 108 109 #define ROUNDUP(size, alignment) round_up(size, alignment) 110 #define cache_op_inner(type, addr, size) \ 111 crypto_flush_cacheline((ulong)addr, size) 112 113 #define IS_NEED_IV(rk_mode) ((rk_mode) != RK_MODE_ECB && \ 114 (rk_mode) != RK_MODE_CMAC && \ 115 (rk_mode) != RK_MODE_CBC_MAC) 116 117 #define IS_NEED_TAG(rk_mode) ((rk_mode) == RK_MODE_CMAC || \ 118 (rk_mode) == RK_MODE_CBC_MAC || \ 119 (rk_mode) == RK_MODE_CCM || \ 120 (rk_mode) == RK_MODE_GCM) 121 122 #define IS_MAC_MODE(rk_mode) ((rk_mode) == RK_MODE_CMAC || \ 123 (rk_mode) == RK_MODE_CBC_MAC) 124 125 #define IS_AE_MODE(rk_mode) ((rk_mode) == RK_MODE_CCM || \ 126 (rk_mode) == RK_MODE_GCM) 127 128 fdt_addr_t crypto_base; 129 static uint32_t g_crypto_version; 130 131 static inline bool is_check_hash_valid(void) 132 { 133 /* crypto < v4 need to check hash valid */ 134 return CRYPTO_MAJOR_VER(g_crypto_version) < CRYPTO_MAJOR_VER_4; 135 } 136 137 static inline bool is_check_tag_valid(void) 138 { 139 /* crypto < v4 need to check hash valid */ 140 return CRYPTO_MAJOR_VER(g_crypto_version) < CRYPTO_MAJOR_VER_4; 141 } 142 143 static inline void word2byte_be(u32 word, u8 *ch) 144 { 145 ch[0] = (word >> 24) & 0xff; 146 ch[1] = (word >> 16) & 0xff; 147 ch[2] = (word >> 8) & 0xff; 148 ch[3] = (word >> 0) & 0xff; 149 } 150 151 static inline u32 byte2word_be(const u8 *ch) 152 { 153 return (*ch << 24) + (*(ch + 1) << 16) + (*(ch + 2) << 8) + *(ch + 3); 154 } 155 156 static inline void clear_regs(u32 base, u32 words) 157 { 158 int i; 159 160 /*clear out register*/ 161 for (i = 0; i < words; i++) 162 crypto_write(0, base + 4 * i); 163 } 164 165 static inline void clear_key_regs(void) 166 { 167 clear_regs(CRYPTO_CH0_KEY_0, CRYPTO_KEY_CHANNEL_NUM * 4); 168 } 169 170 static inline void read_regs(u32 base, u8 *data, u32 data_len) 171 { 172 u8 tmp_buf[4]; 173 u32 i; 174 175 for (i = 0; i < data_len / 4; i++) 176 word2byte_be(crypto_read(base + i * 4), 177 data + i * 4); 178 179 if (data_len % 4) { 180 word2byte_be(crypto_read(base + i * 4), tmp_buf); 181 memcpy(data + i * 4, tmp_buf, data_len % 4); 182 } 183 } 184 185 static inline void write_regs(u32 base, const u8 *data, u32 data_len) 186 { 187 u8 tmp_buf[4]; 188 u32 i; 189 190 for (i = 0; i < data_len / 4; i++, base += 4) 191 crypto_write(byte2word_be(data + i * 4), base); 192 193 if (data_len % 4) { 194 memset(tmp_buf, 0x00, sizeof(tmp_buf)); 195 memcpy((u8 *)tmp_buf, data + i * 4, data_len % 4); 196 crypto_write(byte2word_be(tmp_buf), base); 197 } 198 } 199 200 static inline void write_key_reg(u32 chn, const u8 *key, u32 key_len) 201 { 202 write_regs(CRYPTO_CH0_KEY_0 + chn * 0x10, key, key_len); 203 } 204 205 static inline void set_iv_reg(u32 chn, const u8 *iv, u32 iv_len) 206 { 207 u32 base_iv; 208 209 base_iv = CRYPTO_CH0_IV_0 + chn * 0x10; 210 211 /* clear iv */ 212 clear_regs(base_iv, 4); 213 214 if (!iv || iv_len == 0) 215 return; 216 217 write_regs(base_iv, iv, iv_len); 218 219 crypto_write(iv_len, CRYPTO_CH0_IV_LEN_0 + 4 * chn); 220 } 221 222 static inline void get_iv_reg(u32 chn, u8 *iv, u32 iv_len) 223 { 224 u32 base_iv; 225 226 base_iv = CRYPTO_CH0_IV_0 + chn * 0x10; 227 228 read_regs(base_iv, iv, iv_len); 229 } 230 231 static inline void get_tag_from_reg(u32 chn, u8 *tag, u32 tag_len) 232 { 233 u32 i; 234 u32 chn_base = CRYPTO_CH0_TAG_0 + 0x10 * chn; 235 236 for (i = 0; i < tag_len / 4; i++, chn_base += 4) 237 word2byte_be(crypto_read(chn_base), tag + 4 * i); 238 } 239 240 static int rk_crypto_do_enable_clk(struct udevice *dev, int enable) 241 { 242 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 243 struct clk clk; 244 int i, ret; 245 246 for (i = 0; i < priv->nclocks; i++) { 247 ret = clk_get_by_index(dev, i, &clk); 248 if (ret < 0) { 249 printf("Failed to get clk index %d, ret=%d\n", i, ret); 250 return ret; 251 } 252 253 if (enable) 254 ret = clk_enable(&clk); 255 else 256 ret = clk_disable(&clk); 257 if (ret < 0 && ret != -ENOSYS) { 258 printf("Failed to enable(%d) clk(%ld): ret=%d\n", 259 enable, clk.id, ret); 260 return ret; 261 } 262 } 263 264 return 0; 265 } 266 267 static int rk_crypto_enable_clk(struct udevice *dev) 268 { 269 return rk_crypto_do_enable_clk(dev, 1); 270 } 271 272 static int rk_crypto_disable_clk(struct udevice *dev) 273 { 274 return rk_crypto_do_enable_clk(dev, 0); 275 } 276 277 static u32 crypto_v3_dynamic_cap(void) 278 { 279 u32 capability = 0; 280 u32 ver_reg, i; 281 struct cap_map { 282 u32 ver_offset; 283 u32 mask; 284 u32 cap_bit; 285 }; 286 const struct cap_map cap_tbl[] = { 287 {CRYPTO_HASH_VERSION, CRYPTO_HASH_MD5_FLAG, CRYPTO_MD5}, 288 {CRYPTO_HASH_VERSION, CRYPTO_HASH_SHA1_FLAG, CRYPTO_SHA1}, 289 {CRYPTO_HASH_VERSION, CRYPTO_HASH_SHA256_FLAG, CRYPTO_SHA256}, 290 {CRYPTO_HASH_VERSION, CRYPTO_HASH_SHA512_FLAG, CRYPTO_SHA512}, 291 {CRYPTO_HASH_VERSION, CRYPTO_HASH_SM3_FLAG, CRYPTO_SM3}, 292 293 {CRYPTO_HMAC_VERSION, CRYPTO_HMAC_MD5_FLAG, CRYPTO_HMAC_MD5}, 294 {CRYPTO_HMAC_VERSION, CRYPTO_HMAC_SHA1_FLAG, CRYPTO_HMAC_SHA1}, 295 {CRYPTO_HMAC_VERSION, CRYPTO_HMAC_SHA256_FLAG, CRYPTO_HMAC_SHA256}, 296 {CRYPTO_HMAC_VERSION, CRYPTO_HMAC_SHA512_FLAG, CRYPTO_HMAC_SHA512}, 297 {CRYPTO_HMAC_VERSION, CRYPTO_HMAC_SM3_FLAG, CRYPTO_HMAC_SM3}, 298 299 {CRYPTO_AES_VERSION, CRYPTO_AES256_FLAG, CRYPTO_AES}, 300 {CRYPTO_DES_VERSION, CRYPTO_TDES_FLAG, CRYPTO_DES}, 301 {CRYPTO_SM4_VERSION, CRYPTO_ECB_FLAG, CRYPTO_SM4}, 302 }; 303 304 /* rsa */ 305 capability = CRYPTO_RSA512 | 306 CRYPTO_RSA1024 | 307 CRYPTO_RSA2048 | 308 CRYPTO_RSA3072 | 309 CRYPTO_RSA4096; 310 311 #if CONFIG_IS_ENABLED(ROCKCHIP_EC) 312 capability |= (CRYPTO_SM2 | 313 CRYPTO_ECC_192R1 | 314 CRYPTO_ECC_224R1 | 315 CRYPTO_ECC_256R1); 316 #endif 317 318 for (i = 0; i < ARRAY_SIZE(cap_tbl); i++) { 319 ver_reg = crypto_read(cap_tbl[i].ver_offset); 320 321 if ((ver_reg & cap_tbl[i].mask) == cap_tbl[i].mask) 322 capability |= cap_tbl[i].cap_bit; 323 } 324 325 return capability; 326 } 327 328 static int hw_crypto_reset(void) 329 { 330 u32 val = 0, mask = 0; 331 int ret; 332 333 val = CRYPTO_SW_PKA_RESET | CRYPTO_SW_CC_RESET; 334 mask = val << CRYPTO_WRITE_MASK_SHIFT; 335 336 /* reset pka and crypto modules*/ 337 crypto_write(val | mask, CRYPTO_RST_CTL); 338 339 /* wait reset compelete */ 340 ret = RK_POLL_TIMEOUT(crypto_read(CRYPTO_RST_CTL), RK_CRYPTO_TIMEOUT); 341 342 g_crypto_version = crypto_read(CRYPTO_CRYPTO_VERSION_NEW); 343 344 return ret; 345 } 346 347 static void hw_hash_clean_ctx(struct rk_hash_ctx *ctx) 348 { 349 /* clear hash status */ 350 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 351 352 assert(ctx); 353 assert(ctx->magic == RK_HASH_CTX_MAGIC); 354 355 crypto_hash_cache_free(ctx->hash_cache); 356 357 memset(ctx, 0x00, sizeof(*ctx)); 358 } 359 360 static int rk_hash_init(void *hw_ctx, u32 algo) 361 { 362 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)hw_ctx; 363 u32 reg_ctrl = 0; 364 int ret; 365 366 if (!tmp_ctx) 367 return -EINVAL; 368 369 reg_ctrl = CRYPTO_SW_CC_RESET; 370 crypto_write(reg_ctrl | (reg_ctrl << CRYPTO_WRITE_MASK_SHIFT), 371 CRYPTO_RST_CTL); 372 373 /* wait reset compelete */ 374 ret = RK_POLL_TIMEOUT(crypto_read(CRYPTO_RST_CTL), 375 RK_CRYPTO_TIMEOUT); 376 377 reg_ctrl = 0; 378 tmp_ctx->algo = algo; 379 switch (algo) { 380 case CRYPTO_MD5: 381 case CRYPTO_HMAC_MD5: 382 reg_ctrl |= CRYPTO_MODE_MD5; 383 tmp_ctx->digest_size = 16; 384 break; 385 case CRYPTO_SHA1: 386 case CRYPTO_HMAC_SHA1: 387 reg_ctrl |= CRYPTO_MODE_SHA1; 388 tmp_ctx->digest_size = 20; 389 break; 390 case CRYPTO_SHA256: 391 case CRYPTO_HMAC_SHA256: 392 reg_ctrl |= CRYPTO_MODE_SHA256; 393 tmp_ctx->digest_size = 32; 394 break; 395 case CRYPTO_SHA512: 396 case CRYPTO_HMAC_SHA512: 397 reg_ctrl |= CRYPTO_MODE_SHA512; 398 tmp_ctx->digest_size = 64; 399 break; 400 case CRYPTO_SM3: 401 case CRYPTO_HMAC_SM3: 402 reg_ctrl |= CRYPTO_MODE_SM3; 403 tmp_ctx->digest_size = 32; 404 break; 405 default: 406 ret = -EINVAL; 407 goto exit; 408 } 409 410 /* enable hardware padding */ 411 reg_ctrl |= CRYPTO_HW_PAD_ENABLE; 412 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_HASH_CTL); 413 414 /* FIFO input and output data byte swap */ 415 /* such as B0, B1, B2, B3 -> B3, B2, B1, B0 */ 416 reg_ctrl = CRYPTO_DOUT_BYTESWAP | CRYPTO_DOIN_BYTESWAP; 417 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_FIFO_CTL); 418 419 /* enable src_item_done interrupt */ 420 crypto_write(0, CRYPTO_DMA_INT_EN); 421 422 tmp_ctx->magic = RK_HASH_CTX_MAGIC; 423 424 return 0; 425 exit: 426 /* clear hash setting if init failed */ 427 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 428 429 return ret; 430 } 431 432 static int rk_hash_direct_calc(void *hw_data, const u8 *data, 433 u32 data_len, u8 *started_flag, u8 is_last) 434 { 435 struct rockchip_crypto_priv *priv = hw_data; 436 struct rk_hash_ctx *hash_ctx = priv->hw_ctx; 437 struct crypto_lli_desc *lli = &hash_ctx->data_lli; 438 int ret = -EINVAL; 439 u32 tmp = 0, mask = 0; 440 441 assert(IS_ALIGNED((ulong)data, DATA_ADDR_ALIGN_SIZE)); 442 assert(is_last || IS_ALIGNED(data_len, DATA_LEN_ALIGN_SIZE)); 443 444 debug("%s: data = %p, len = %u, s = %x, l = %x\n", 445 __func__, data, data_len, *started_flag, is_last); 446 447 memset(lli, 0x00, sizeof(*lli)); 448 lli->src_addr = (u32)virt_to_phys(data); 449 lli->src_len = data_len; 450 lli->dma_ctrl = LLI_DMA_CTRL_SRC_DONE; 451 452 if (is_last) { 453 lli->user_define |= LLI_USER_STRING_LAST; 454 lli->dma_ctrl |= LLI_DMA_CTRL_LAST; 455 } else { 456 lli->next_addr = (u32)virt_to_phys(lli); 457 lli->dma_ctrl |= LLI_DMA_CTRL_PAUSE; 458 } 459 460 if (!(*started_flag)) { 461 lli->user_define |= 462 (LLI_USER_STRING_START | LLI_USER_CIPHER_START); 463 crypto_write((u32)virt_to_phys(lli), CRYPTO_DMA_LLI_ADDR); 464 crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) | 465 CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL); 466 tmp = CRYPTO_DMA_START; 467 *started_flag = 1; 468 } else { 469 tmp = CRYPTO_DMA_RESTART; 470 } 471 472 /* flush cache */ 473 crypto_flush_cacheline((ulong)lli, sizeof(*lli)); 474 crypto_flush_cacheline((ulong)data, data_len); 475 476 /* start calculate */ 477 crypto_write(tmp << CRYPTO_WRITE_MASK_SHIFT | tmp, 478 CRYPTO_DMA_CTL); 479 480 /* mask CRYPTO_SYNC_LOCKSTEP_INT_ST flag */ 481 mask = ~(mask | CRYPTO_SYNC_LOCKSTEP_INT_ST); 482 483 /* wait calc ok */ 484 ret = RK_POLL_TIMEOUT(!(crypto_read(CRYPTO_DMA_INT_ST) & mask), 485 RK_CRYPTO_TIMEOUT); 486 487 /* clear interrupt status */ 488 tmp = crypto_read(CRYPTO_DMA_INT_ST); 489 crypto_write(tmp, CRYPTO_DMA_INT_ST); 490 491 if ((tmp & mask) != CRYPTO_SRC_ITEM_DONE_INT_ST && 492 (tmp & mask) != CRYPTO_ZERO_LEN_INT_ST) { 493 ret = -EFAULT; 494 debug("[%s] %d: CRYPTO_DMA_INT_ST = 0x%x\n", 495 __func__, __LINE__, tmp); 496 goto exit; 497 } 498 499 priv->length += data_len; 500 exit: 501 return ret; 502 } 503 504 int rk_hash_update(void *ctx, const u8 *data, u32 data_len) 505 { 506 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 507 int ret = -EINVAL; 508 509 debug("\n"); 510 if (!tmp_ctx || !data) 511 goto exit; 512 513 if (tmp_ctx->digest_size == 0 || tmp_ctx->magic != RK_HASH_CTX_MAGIC) 514 goto exit; 515 516 ret = crypto_hash_update_with_cache(tmp_ctx->hash_cache, 517 data, data_len); 518 519 exit: 520 /* free lli list */ 521 if (ret) 522 hw_hash_clean_ctx(tmp_ctx); 523 524 return ret; 525 } 526 527 int rk_hash_final(void *ctx, u8 *digest, size_t len) 528 { 529 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 530 int ret = 0; 531 532 if (!digest) 533 goto exit; 534 535 if (!tmp_ctx || 536 tmp_ctx->digest_size == 0 || 537 len > tmp_ctx->digest_size || 538 tmp_ctx->magic != RK_HASH_CTX_MAGIC) { 539 goto exit; 540 } 541 542 if(is_check_hash_valid()) { 543 /* wait hash value ok */ 544 ret = RK_POLL_TIMEOUT(!crypto_read(CRYPTO_HASH_VALID), 545 RK_CRYPTO_TIMEOUT); 546 } 547 548 read_regs(CRYPTO_HASH_DOUT_0, digest, len); 549 550 /* clear hash status */ 551 crypto_write(CRYPTO_HASH_IS_VALID, CRYPTO_HASH_VALID); 552 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 553 554 exit: 555 556 return ret; 557 } 558 559 static u32 rockchip_crypto_capability(struct udevice *dev) 560 { 561 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 562 u32 capability, mask = 0; 563 564 capability = priv->soc_data->capability; 565 566 #if !(CONFIG_IS_ENABLED(ROCKCHIP_CIPHER)) 567 mask |= (CRYPTO_DES | CRYPTO_AES | CRYPTO_SM4); 568 #endif 569 570 #if !(CONFIG_IS_ENABLED(ROCKCHIP_HMAC)) 571 mask |= (CRYPTO_HMAC_MD5 | CRYPTO_HMAC_SHA1 | CRYPTO_HMAC_SHA256 | 572 CRYPTO_HMAC_SHA512 | CRYPTO_HMAC_SM3); 573 #endif 574 575 #if !(CONFIG_IS_ENABLED(ROCKCHIP_RSA)) 576 mask |= (CRYPTO_RSA512 | CRYPTO_RSA1024 | CRYPTO_RSA2048 | 577 CRYPTO_RSA3072 | CRYPTO_RSA4096); 578 #endif 579 580 return capability & (~mask); 581 } 582 583 static int rockchip_crypto_sha_init(struct udevice *dev, sha_context *ctx) 584 { 585 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 586 struct rk_hash_ctx *hash_ctx = priv->hw_ctx; 587 int ret = 0; 588 589 if (!ctx) 590 return -EINVAL; 591 592 memset(hash_ctx, 0x00, sizeof(*hash_ctx)); 593 594 priv->length = 0; 595 596 hash_ctx->hash_cache = crypto_hash_cache_alloc(rk_hash_direct_calc, 597 priv, ctx->length, 598 DATA_ADDR_ALIGN_SIZE, 599 DATA_LEN_ALIGN_SIZE); 600 if (!hash_ctx->hash_cache) 601 return -EFAULT; 602 603 rk_crypto_enable_clk(dev); 604 ret = rk_hash_init(hash_ctx, ctx->algo); 605 if (ret) 606 rk_crypto_disable_clk(dev); 607 608 return ret; 609 } 610 611 static int rockchip_crypto_sha_update(struct udevice *dev, 612 u32 *input, u32 len) 613 { 614 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 615 int ret, i; 616 u8 *p; 617 618 if (!len) { 619 ret = -EINVAL; 620 goto exit; 621 } 622 623 p = (u8 *)input; 624 625 for (i = 0; i < len / HASH_UPDATE_LIMIT; i++, p += HASH_UPDATE_LIMIT) { 626 ret = rk_hash_update(priv->hw_ctx, p, HASH_UPDATE_LIMIT); 627 if (ret) 628 goto exit; 629 } 630 631 if (len % HASH_UPDATE_LIMIT) 632 ret = rk_hash_update(priv->hw_ctx, p, len % HASH_UPDATE_LIMIT); 633 634 exit: 635 if (ret) 636 rk_crypto_disable_clk(dev); 637 638 return ret; 639 } 640 641 static int rockchip_crypto_sha_final(struct udevice *dev, 642 sha_context *ctx, u8 *output) 643 { 644 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 645 u32 nbits; 646 int ret; 647 648 nbits = crypto_algo_nbits(ctx->algo); 649 650 if (priv->length != ctx->length) { 651 printf("total length(0x%08x) != init length(0x%08x)!\n", 652 priv->length, ctx->length); 653 ret = -EIO; 654 goto exit; 655 } 656 657 ret = rk_hash_final(priv->hw_ctx, (u8 *)output, BITS2BYTE(nbits)); 658 659 exit: 660 hw_hash_clean_ctx(priv->hw_ctx); 661 rk_crypto_disable_clk(dev); 662 663 return ret; 664 } 665 666 #if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) 667 int rk_hmac_init(void *hw_ctx, u32 algo, u8 *key, u32 key_len) 668 { 669 u32 reg_ctrl = 0; 670 int ret; 671 672 if (!key || !key_len || key_len > 64) 673 return -EINVAL; 674 675 clear_key_regs(); 676 677 write_key_reg(0, key, key_len); 678 679 ret = rk_hash_init(hw_ctx, algo); 680 if (ret) 681 return ret; 682 683 reg_ctrl = crypto_read(CRYPTO_HASH_CTL) | CRYPTO_HMAC_ENABLE; 684 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_HASH_CTL); 685 686 return ret; 687 } 688 689 static int rockchip_crypto_hmac_init(struct udevice *dev, 690 sha_context *ctx, u8 *key, u32 key_len) 691 { 692 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 693 struct rk_hash_ctx *hash_ctx = priv->hw_ctx; 694 int ret = 0; 695 696 if (!ctx) 697 return -EINVAL; 698 699 memset(hash_ctx, 0x00, sizeof(*hash_ctx)); 700 701 priv->length = 0; 702 703 hash_ctx->hash_cache = crypto_hash_cache_alloc(rk_hash_direct_calc, 704 priv, ctx->length, 705 DATA_ADDR_ALIGN_SIZE, 706 DATA_LEN_ALIGN_SIZE); 707 if (!hash_ctx->hash_cache) 708 return -EFAULT; 709 710 rk_crypto_enable_clk(dev); 711 ret = rk_hmac_init(priv->hw_ctx, ctx->algo, key, key_len); 712 if (ret) 713 rk_crypto_disable_clk(dev); 714 715 return ret; 716 } 717 718 static int rockchip_crypto_hmac_update(struct udevice *dev, 719 u32 *input, u32 len) 720 { 721 return rockchip_crypto_sha_update(dev, input, len); 722 } 723 724 static int rockchip_crypto_hmac_final(struct udevice *dev, 725 sha_context *ctx, u8 *output) 726 { 727 return rockchip_crypto_sha_final(dev, ctx, output); 728 } 729 730 #endif 731 732 #if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) 733 static u8 g_key_chn; 734 735 static const u32 rk_mode2bc_mode[RK_MODE_MAX] = { 736 [RK_MODE_ECB] = CRYPTO_BC_ECB, 737 [RK_MODE_CBC] = CRYPTO_BC_CBC, 738 [RK_MODE_CTS] = CRYPTO_BC_CTS, 739 [RK_MODE_CTR] = CRYPTO_BC_CTR, 740 [RK_MODE_CFB] = CRYPTO_BC_CFB, 741 [RK_MODE_OFB] = CRYPTO_BC_OFB, 742 [RK_MODE_XTS] = CRYPTO_BC_XTS, 743 [RK_MODE_CCM] = CRYPTO_BC_CCM, 744 [RK_MODE_GCM] = CRYPTO_BC_GCM, 745 [RK_MODE_CMAC] = CRYPTO_BC_CMAC, 746 [RK_MODE_CBC_MAC] = CRYPTO_BC_CBC_MAC, 747 }; 748 749 static inline void set_pc_len_reg(u32 chn, u64 pc_len) 750 { 751 u32 chn_base = CRYPTO_CH0_PC_LEN_0 + chn * 0x08; 752 753 crypto_write(pc_len & 0xffffffff, chn_base); 754 crypto_write(pc_len >> 32, chn_base + 4); 755 } 756 757 static inline void set_aad_len_reg(u32 chn, u64 pc_len) 758 { 759 u32 chn_base = CRYPTO_CH0_AAD_LEN_0 + chn * 0x08; 760 761 crypto_write(pc_len & 0xffffffff, chn_base); 762 crypto_write(pc_len >> 32, chn_base + 4); 763 } 764 765 static inline bool is_des_mode(u32 rk_mode) 766 { 767 return (rk_mode == RK_MODE_ECB || 768 rk_mode == RK_MODE_CBC || 769 rk_mode == RK_MODE_CFB || 770 rk_mode == RK_MODE_OFB); 771 } 772 773 static void dump_crypto_state(struct crypto_lli_desc *desc, 774 u32 tmp, u32 expt_int, 775 const u8 *in, const u8 *out, 776 u32 len, int ret) 777 { 778 IMSG("%s\n", ret == -ETIME ? "timeout" : "dismatch"); 779 780 IMSG("CRYPTO_DMA_INT_ST = %08x, expect_int = %08x\n", 781 tmp, expt_int); 782 IMSG("data desc = %p\n", desc); 783 IMSG("\taddr_in = [%08x <=> %08x]\n", 784 desc->src_addr, (u32)virt_to_phys(in)); 785 IMSG("\taddr_out = [%08x <=> %08x]\n", 786 desc->dst_addr, (u32)virt_to_phys(out)); 787 IMSG("\tsrc_len = [%08x <=> %08x]\n", 788 desc->src_len, (u32)len); 789 IMSG("\tdst_len = %08x\n", desc->dst_len); 790 IMSG("\tdma_ctl = %08x\n", desc->dma_ctrl); 791 IMSG("\tuser_define = %08x\n", desc->user_define); 792 793 IMSG("\n\nDMA CRYPTO_DMA_LLI_ADDR status = %08x\n", 794 crypto_read(CRYPTO_DMA_LLI_ADDR)); 795 IMSG("DMA CRYPTO_DMA_ST status = %08x\n", 796 crypto_read(CRYPTO_DMA_ST)); 797 IMSG("DMA CRYPTO_DMA_STATE status = %08x\n", 798 crypto_read(CRYPTO_DMA_STATE)); 799 IMSG("DMA CRYPTO_DMA_LLI_RADDR status = %08x\n", 800 crypto_read(CRYPTO_DMA_LLI_RADDR)); 801 IMSG("DMA CRYPTO_DMA_SRC_RADDR status = %08x\n", 802 crypto_read(CRYPTO_DMA_SRC_RADDR)); 803 IMSG("DMA CRYPTO_DMA_DST_RADDR status = %08x\n", 804 crypto_read(CRYPTO_DMA_DST_RADDR)); 805 IMSG("DMA CRYPTO_CIPHER_ST status = %08x\n", 806 crypto_read(CRYPTO_CIPHER_ST)); 807 IMSG("DMA CRYPTO_CIPHER_STATE status = %08x\n", 808 crypto_read(CRYPTO_CIPHER_STATE)); 809 IMSG("DMA CRYPTO_TAG_VALID status = %08x\n", 810 crypto_read(CRYPTO_TAG_VALID)); 811 IMSG("LOCKSTEP status = %08x\n\n", 812 crypto_read(0x618)); 813 814 IMSG("dst %dbyte not transferred\n", 815 desc->dst_addr + desc->dst_len - 816 crypto_read(CRYPTO_DMA_DST_RADDR)); 817 } 818 819 static int ccm128_set_iv_reg(u32 chn, const u8 *nonce, u32 nlen) 820 { 821 u8 iv_buf[AES_BLOCK_SIZE]; 822 u32 L; 823 824 memset(iv_buf, 0x00, sizeof(iv_buf)); 825 826 L = 15 - nlen; 827 iv_buf[0] = ((u8)(L - 1) & 7); 828 829 /* the L parameter */ 830 L = iv_buf[0] & 7; 831 832 /* nonce is too short */ 833 if (nlen < (14 - L)) 834 return -EINVAL; 835 836 /* clear aad flag */ 837 iv_buf[0] &= ~0x40; 838 memcpy(&iv_buf[1], nonce, 14 - L); 839 840 set_iv_reg(chn, iv_buf, AES_BLOCK_SIZE); 841 842 return 0; 843 } 844 845 static void ccm_aad_padding(u32 aad_len, u8 *padding, u32 *padding_size) 846 { 847 u32 i; 848 849 if (aad_len == 0) { 850 *padding_size = 0; 851 return; 852 } 853 854 i = aad_len < (0x10000 - 0x100) ? 2 : 6; 855 856 if (i == 2) { 857 padding[0] = (u8)(aad_len >> 8); 858 padding[1] = (u8)aad_len; 859 } else { 860 padding[0] = 0xFF; 861 padding[1] = 0xFE; 862 padding[2] = (u8)(aad_len >> 24); 863 padding[3] = (u8)(aad_len >> 16); 864 padding[4] = (u8)(aad_len >> 8); 865 } 866 867 *padding_size = i; 868 } 869 870 static int ccm_compose_aad_iv(u8 *aad_iv, u32 data_len, u32 aad_len, u32 tag_size) 871 { 872 aad_iv[0] |= ((u8)(((tag_size - 2) / 2) & 7) << 3); 873 874 aad_iv[12] = (u8)(data_len >> 24); 875 aad_iv[13] = (u8)(data_len >> 16); 876 aad_iv[14] = (u8)(data_len >> 8); 877 aad_iv[15] = (u8)data_len; 878 879 if (aad_len) 880 aad_iv[0] |= 0x40; //set aad flag 881 882 return 0; 883 } 884 885 static int hw_cipher_init(u32 chn, const u8 *key, const u8 *twk_key, 886 u32 key_len, const u8 *iv, u32 iv_len, 887 u32 algo, u32 mode, bool enc) 888 { 889 u32 rk_mode = RK_GET_RK_MODE(mode); 890 u32 key_chn_sel = chn; 891 u32 reg_ctrl = 0; 892 893 IMSG("%s: key addr is %p, key_len is %d, iv addr is %p", 894 __func__, key, key_len, iv); 895 if (rk_mode >= RK_MODE_MAX) 896 return -EINVAL; 897 898 switch (algo) { 899 case CRYPTO_DES: 900 if (key_len > DES_BLOCK_SIZE) 901 reg_ctrl |= CRYPTO_BC_TDES; 902 else 903 reg_ctrl |= CRYPTO_BC_DES; 904 break; 905 case CRYPTO_AES: 906 reg_ctrl |= CRYPTO_BC_AES; 907 break; 908 case CRYPTO_SM4: 909 reg_ctrl |= CRYPTO_BC_SM4; 910 break; 911 default: 912 return -EINVAL; 913 } 914 915 if (algo == CRYPTO_AES || algo == CRYPTO_SM4) { 916 switch (key_len) { 917 case AES_KEYSIZE_128: 918 reg_ctrl |= CRYPTO_BC_128_bit_key; 919 break; 920 case AES_KEYSIZE_192: 921 reg_ctrl |= CRYPTO_BC_192_bit_key; 922 break; 923 case AES_KEYSIZE_256: 924 reg_ctrl |= CRYPTO_BC_256_bit_key; 925 break; 926 default: 927 return -EINVAL; 928 } 929 } 930 931 reg_ctrl |= rk_mode2bc_mode[rk_mode]; 932 if (!enc) 933 reg_ctrl |= CRYPTO_BC_DECRYPT; 934 935 /* write key data to reg */ 936 write_key_reg(key_chn_sel, key, key_len); 937 938 /* write twk key for xts mode */ 939 if (rk_mode == RK_MODE_XTS) 940 write_key_reg(key_chn_sel + 4, twk_key, key_len); 941 942 /* set iv reg */ 943 if (rk_mode == RK_MODE_CCM) 944 ccm128_set_iv_reg(chn, iv, iv_len); 945 else 946 set_iv_reg(chn, iv, iv_len); 947 948 /* din_swap set 1, dout_swap set 1, default 1. */ 949 crypto_write(0x00030003, CRYPTO_FIFO_CTL); 950 crypto_write(0, CRYPTO_DMA_INT_EN); 951 952 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_BC_CTL); 953 954 return 0; 955 } 956 957 static int hw_cipher_crypt(const u8 *in, u8 *out, u64 len, 958 const u8 *aad, u32 aad_len, 959 u8 *tag, u32 tag_len, u32 mode) 960 { 961 struct crypto_lli_desc *data_desc = NULL, *aad_desc = NULL; 962 u8 *dma_in = NULL, *dma_out = NULL, *aad_tmp = NULL; 963 u32 rk_mode = RK_GET_RK_MODE(mode); 964 u32 reg_ctrl = 0, tmp_len = 0; 965 u32 expt_int = 0, mask = 0; 966 u32 key_chn = g_key_chn; 967 u32 tmp, dst_len = 0; 968 int ret = -1; 969 970 if (rk_mode == RK_MODE_CTS && len <= AES_BLOCK_SIZE) { 971 printf("CTS mode length %u < 16Byte\n", (u32)len); 972 return -EINVAL; 973 } 974 975 tmp_len = (rk_mode == RK_MODE_CTR) ? ROUNDUP(len, AES_BLOCK_SIZE) : len; 976 977 data_desc = align_malloc(sizeof(*data_desc), LLI_ADDR_ALIGN_SIZE); 978 if (!data_desc) 979 goto exit; 980 981 if (IS_ALIGNED((ulong)in, DATA_ADDR_ALIGN_SIZE) && tmp_len == len) 982 dma_in = (void *)in; 983 else 984 dma_in = align_malloc(tmp_len, DATA_ADDR_ALIGN_SIZE); 985 if (!dma_in) 986 goto exit; 987 988 if (out) { 989 if (IS_ALIGNED((ulong)out, DATA_ADDR_ALIGN_SIZE) && 990 tmp_len == len) 991 dma_out = out; 992 else 993 dma_out = align_malloc(tmp_len, DATA_ADDR_ALIGN_SIZE); 994 if (!dma_out) 995 goto exit; 996 dst_len = tmp_len; 997 } 998 999 memset(data_desc, 0x00, sizeof(*data_desc)); 1000 if (dma_in != in) 1001 memcpy(dma_in, in, len); 1002 1003 data_desc->src_addr = (u32)virt_to_phys(dma_in); 1004 data_desc->src_len = tmp_len; 1005 data_desc->dst_addr = (u32)virt_to_phys(dma_out); 1006 data_desc->dst_len = dst_len; 1007 data_desc->dma_ctrl = LLI_DMA_CTRL_LAST; 1008 1009 if (IS_MAC_MODE(rk_mode)) { 1010 expt_int = CRYPTO_LIST_DONE_INT_ST; 1011 data_desc->dma_ctrl |= LLI_DMA_CTRL_LIST_DONE; 1012 } else { 1013 expt_int = CRYPTO_DST_ITEM_DONE_INT_ST; 1014 data_desc->dma_ctrl |= LLI_DMA_CTRL_DST_DONE; 1015 } 1016 1017 data_desc->user_define = LLI_USER_CIPHER_START | 1018 LLI_USER_STRING_START | 1019 LLI_USER_STRING_LAST | 1020 (key_chn << 4); 1021 crypto_write((u32)virt_to_phys(data_desc), CRYPTO_DMA_LLI_ADDR); 1022 1023 if (rk_mode == RK_MODE_CCM || rk_mode == RK_MODE_GCM) { 1024 u32 aad_tmp_len = 0; 1025 1026 aad_desc = align_malloc(sizeof(*aad_desc), LLI_ADDR_ALIGN_SIZE); 1027 if (!aad_desc) 1028 goto exit; 1029 1030 memset(aad_desc, 0x00, sizeof(*aad_desc)); 1031 aad_desc->next_addr = (u32)virt_to_phys(data_desc); 1032 aad_desc->user_define = LLI_USER_CIPHER_START | 1033 LLI_USER_STRING_START | 1034 LLI_USER_STRING_LAST | 1035 LLI_USER_STRING_AAD | 1036 (key_chn << 4); 1037 1038 if (rk_mode == RK_MODE_CCM) { 1039 u8 padding[AES_BLOCK_SIZE]; 1040 u32 padding_size = 0; 1041 1042 memset(padding, 0x00, sizeof(padding)); 1043 ccm_aad_padding(aad_len, padding, &padding_size); 1044 1045 aad_tmp_len = aad_len + AES_BLOCK_SIZE + padding_size; 1046 aad_tmp_len = ROUNDUP(aad_tmp_len, AES_BLOCK_SIZE); 1047 aad_tmp = align_malloc(aad_tmp_len, 1048 DATA_ADDR_ALIGN_SIZE); 1049 if (!aad_tmp) 1050 goto exit; 1051 1052 /* clear last block */ 1053 memset(aad_tmp + aad_tmp_len - AES_BLOCK_SIZE, 1054 0x00, AES_BLOCK_SIZE); 1055 1056 /* read iv data from reg */ 1057 get_iv_reg(key_chn, aad_tmp, AES_BLOCK_SIZE); 1058 ccm_compose_aad_iv(aad_tmp, tmp_len, aad_len, tag_len); 1059 memcpy(aad_tmp + AES_BLOCK_SIZE, padding, padding_size); 1060 1061 memcpy(aad_tmp + AES_BLOCK_SIZE + padding_size, 1062 aad, aad_len); 1063 } else { 1064 aad_tmp_len = aad_len; 1065 if (IS_ALIGNED((ulong)aad, DATA_ADDR_ALIGN_SIZE)) { 1066 aad_tmp = (void *)aad; 1067 } else { 1068 aad_tmp = align_malloc(aad_tmp_len, 1069 DATA_ADDR_ALIGN_SIZE); 1070 if (!aad_tmp) 1071 goto exit; 1072 1073 memcpy(aad_tmp, aad, aad_tmp_len); 1074 } 1075 1076 set_aad_len_reg(key_chn, aad_tmp_len); 1077 set_pc_len_reg(key_chn, tmp_len); 1078 } 1079 1080 aad_desc->src_addr = (u32)virt_to_phys(aad_tmp); 1081 aad_desc->src_len = aad_tmp_len; 1082 1083 if (aad_tmp_len) { 1084 data_desc->user_define = LLI_USER_STRING_START | 1085 LLI_USER_STRING_LAST | 1086 (key_chn << 4); 1087 crypto_write((u32)virt_to_phys(aad_desc), CRYPTO_DMA_LLI_ADDR); 1088 cache_op_inner(DCACHE_AREA_CLEAN, aad_tmp, aad_tmp_len); 1089 cache_op_inner(DCACHE_AREA_CLEAN, aad_desc, sizeof(*aad_desc)); 1090 } 1091 } 1092 1093 cache_op_inner(DCACHE_AREA_CLEAN, data_desc, sizeof(*data_desc)); 1094 cache_op_inner(DCACHE_AREA_CLEAN, dma_in, tmp_len); 1095 cache_op_inner(DCACHE_AREA_INVALIDATE, dma_out, tmp_len); 1096 1097 /* din_swap set 1, dout_swap set 1, default 1. */ 1098 crypto_write(0x00030003, CRYPTO_FIFO_CTL); 1099 crypto_write(0, CRYPTO_DMA_INT_EN); 1100 1101 reg_ctrl = crypto_read(CRYPTO_BC_CTL) | CRYPTO_BC_ENABLE; 1102 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_BC_CTL); 1103 crypto_write(0x00010001, CRYPTO_DMA_CTL);//start 1104 1105 mask = ~(mask | CRYPTO_SYNC_LOCKSTEP_INT_ST); 1106 1107 /* wait calc ok */ 1108 ret = RK_POLL_TIMEOUT(!(crypto_read(CRYPTO_DMA_INT_ST) & mask), 1109 RK_CRYPTO_TIMEOUT); 1110 tmp = crypto_read(CRYPTO_DMA_INT_ST); 1111 crypto_write(tmp, CRYPTO_DMA_INT_ST); 1112 1113 if ((tmp & mask) == expt_int) { 1114 if (out && out != dma_out) 1115 memcpy(out, dma_out, len); 1116 1117 if (IS_NEED_TAG(rk_mode)) { 1118 ret = WAIT_TAG_VALID(key_chn, RK_CRYPTO_TIMEOUT); 1119 get_tag_from_reg(key_chn, tag, AES_BLOCK_SIZE); 1120 } 1121 } else { 1122 dump_crypto_state(data_desc, tmp, expt_int, in, out, len, ret); 1123 ret = -1; 1124 } 1125 1126 exit: 1127 crypto_write(0xffff0000, CRYPTO_BC_CTL);//bc_ctl disable 1128 align_free(data_desc); 1129 align_free(aad_desc); 1130 if (dma_in != in) 1131 align_free(dma_in); 1132 if (out && dma_out != out) 1133 align_free(dma_out); 1134 if (aad && aad != aad_tmp) 1135 align_free(aad_tmp); 1136 1137 return ret; 1138 } 1139 1140 static int hw_aes_init(u32 chn, const u8 *key, const u8 *twk_key, u32 key_len, 1141 const u8 *iv, u32 iv_len, u32 mode, bool enc) 1142 { 1143 u32 rk_mode = RK_GET_RK_MODE(mode); 1144 1145 if (rk_mode > RK_MODE_XTS) 1146 return -EINVAL; 1147 1148 if (iv_len > AES_BLOCK_SIZE) 1149 return -EINVAL; 1150 1151 if (IS_NEED_IV(rk_mode)) { 1152 if (!iv || iv_len != AES_BLOCK_SIZE) 1153 return -EINVAL; 1154 } else { 1155 iv_len = 0; 1156 } 1157 1158 if (rk_mode == RK_MODE_XTS) { 1159 if (key_len != AES_KEYSIZE_128 && key_len != AES_KEYSIZE_256) 1160 return -EINVAL; 1161 1162 if (!key || !twk_key) 1163 return -EINVAL; 1164 } else { 1165 if (key_len != AES_KEYSIZE_128 && 1166 key_len != AES_KEYSIZE_192 && 1167 key_len != AES_KEYSIZE_256) 1168 return -EINVAL; 1169 } 1170 1171 return hw_cipher_init(chn, key, twk_key, key_len, iv, iv_len, 1172 CRYPTO_AES, mode, enc); 1173 } 1174 1175 static int hw_sm4_init(u32 chn, const u8 *key, const u8 *twk_key, u32 key_len, 1176 const u8 *iv, u32 iv_len, u32 mode, bool enc) 1177 { 1178 u32 rk_mode = RK_GET_RK_MODE(mode); 1179 1180 if (rk_mode > RK_MODE_XTS) 1181 return -EINVAL; 1182 1183 if (iv_len > SM4_BLOCK_SIZE || key_len != SM4_KEYSIZE) 1184 return -EINVAL; 1185 1186 if (IS_NEED_IV(rk_mode)) { 1187 if (!iv || iv_len != SM4_BLOCK_SIZE) 1188 return -EINVAL; 1189 } else { 1190 iv_len = 0; 1191 } 1192 1193 if (rk_mode == RK_MODE_XTS) { 1194 if (!key || !twk_key) 1195 return -EINVAL; 1196 } 1197 1198 return hw_cipher_init(chn, key, twk_key, key_len, iv, iv_len, 1199 CRYPTO_SM4, mode, enc); 1200 } 1201 1202 int rk_crypto_des(struct udevice *dev, u32 mode, const u8 *key, u32 key_len, 1203 const u8 *iv, const u8 *in, u8 *out, u32 len, bool enc) 1204 { 1205 u32 rk_mode = RK_GET_RK_MODE(mode); 1206 u8 tmp_key[24]; 1207 int ret; 1208 1209 if (!is_des_mode(rk_mode)) 1210 return -EINVAL; 1211 1212 if (key_len == DES_BLOCK_SIZE || key_len == 3 * DES_BLOCK_SIZE) { 1213 memcpy(tmp_key, key, key_len); 1214 } else if (key_len == 2 * DES_BLOCK_SIZE) { 1215 memcpy(tmp_key, key, 16); 1216 memcpy(tmp_key + 16, key, 8); 1217 key_len = 3 * DES_BLOCK_SIZE; 1218 } else { 1219 return -EINVAL; 1220 } 1221 1222 ret = hw_cipher_init(0, tmp_key, NULL, key_len, iv, DES_BLOCK_SIZE, 1223 CRYPTO_DES, mode, enc); 1224 if (ret) 1225 goto exit; 1226 1227 ret = hw_cipher_crypt(in, out, len, NULL, 0, 1228 NULL, 0, mode); 1229 1230 exit: 1231 return ret; 1232 } 1233 1234 int rk_crypto_aes(struct udevice *dev, u32 mode, 1235 const u8 *key, const u8 *twk_key, u32 key_len, 1236 const u8 *iv, u32 iv_len, 1237 const u8 *in, u8 *out, u32 len, bool enc) 1238 { 1239 int ret; 1240 1241 /* RV1126/RV1109 do not support aes-192 */ 1242 #if defined(CONFIG_ROCKCHIP_RV1126) 1243 if (key_len == AES_KEYSIZE_192) 1244 return -EINVAL; 1245 #endif 1246 1247 ret = hw_aes_init(0, key, twk_key, key_len, iv, iv_len, mode, enc); 1248 if (ret) 1249 return ret; 1250 1251 return hw_cipher_crypt(in, out, len, NULL, 0, 1252 NULL, 0, mode); 1253 } 1254 1255 int rk_crypto_sm4(struct udevice *dev, u32 mode, 1256 const u8 *key, const u8 *twk_key, u32 key_len, 1257 const u8 *iv, u32 iv_len, 1258 const u8 *in, u8 *out, u32 len, bool enc) 1259 { 1260 int ret; 1261 1262 ret = hw_sm4_init(0, key, twk_key, key_len, iv, iv_len, mode, enc); 1263 if (ret) 1264 return ret; 1265 1266 return hw_cipher_crypt(in, out, len, NULL, 0, NULL, 0, mode); 1267 } 1268 1269 int rockchip_crypto_cipher(struct udevice *dev, cipher_context *ctx, 1270 const u8 *in, u8 *out, u32 len, bool enc) 1271 { 1272 int ret; 1273 1274 rk_crypto_enable_clk(dev); 1275 1276 switch (ctx->algo) { 1277 case CRYPTO_DES: 1278 ret = rk_crypto_des(dev, ctx->mode, ctx->key, ctx->key_len, 1279 ctx->iv, in, out, len, enc); 1280 break; 1281 case CRYPTO_AES: 1282 ret = rk_crypto_aes(dev, ctx->mode, 1283 ctx->key, ctx->twk_key, ctx->key_len, 1284 ctx->iv, ctx->iv_len, in, out, len, enc); 1285 break; 1286 case CRYPTO_SM4: 1287 ret = rk_crypto_sm4(dev, ctx->mode, 1288 ctx->key, ctx->twk_key, ctx->key_len, 1289 ctx->iv, ctx->iv_len, in, out, len, enc); 1290 break; 1291 default: 1292 ret = -EINVAL; 1293 break; 1294 } 1295 1296 rk_crypto_disable_clk(dev); 1297 1298 return ret; 1299 } 1300 1301 int rk_crypto_mac(struct udevice *dev, u32 algo, u32 mode, 1302 const u8 *key, u32 key_len, 1303 const u8 *in, u32 len, u8 *tag) 1304 { 1305 u32 rk_mode = RK_GET_RK_MODE(mode); 1306 int ret; 1307 1308 if (!IS_MAC_MODE(rk_mode)) 1309 return -EINVAL; 1310 1311 if (algo != CRYPTO_AES && algo != CRYPTO_SM4) 1312 return -EINVAL; 1313 1314 /* RV1126/RV1109 do not support aes-192 */ 1315 #if defined(CONFIG_ROCKCHIP_RV1126) 1316 if (algo == CRYPTO_AES && key_len == AES_KEYSIZE_192) 1317 return -EINVAL; 1318 #endif 1319 1320 ret = hw_cipher_init(g_key_chn, key, NULL, key_len, NULL, 0, 1321 algo, mode, true); 1322 if (ret) 1323 return ret; 1324 1325 return hw_cipher_crypt(in, NULL, len, NULL, 0, 1326 tag, AES_BLOCK_SIZE, mode); 1327 } 1328 1329 int rockchip_crypto_mac(struct udevice *dev, cipher_context *ctx, 1330 const u8 *in, u32 len, u8 *tag) 1331 { 1332 int ret = 0; 1333 1334 rk_crypto_enable_clk(dev); 1335 1336 ret = rk_crypto_mac(dev, ctx->algo, ctx->mode, 1337 ctx->key, ctx->key_len, in, len, tag); 1338 1339 rk_crypto_disable_clk(dev); 1340 1341 return ret; 1342 } 1343 1344 int rk_crypto_ae(struct udevice *dev, u32 algo, u32 mode, 1345 const u8 *key, u32 key_len, const u8 *nonce, u32 nonce_len, 1346 const u8 *in, u32 len, const u8 *aad, u32 aad_len, 1347 u8 *out, u8 *tag) 1348 { 1349 u32 rk_mode = RK_GET_RK_MODE(mode); 1350 int ret; 1351 1352 if (!IS_AE_MODE(rk_mode)) 1353 return -EINVAL; 1354 1355 if (len == 0) 1356 return -EINVAL; 1357 1358 if (algo != CRYPTO_AES && algo != CRYPTO_SM4) 1359 return -EINVAL; 1360 1361 /* RV1126/RV1109 do not support aes-192 */ 1362 #if defined(CONFIG_ROCKCHIP_RV1126) 1363 if (algo == CRYPTO_AES && key_len == AES_KEYSIZE_192) 1364 return -EINVAL; 1365 #endif 1366 1367 ret = hw_cipher_init(g_key_chn, key, NULL, key_len, nonce, nonce_len, 1368 algo, mode, true); 1369 if (ret) 1370 return ret; 1371 1372 return hw_cipher_crypt(in, out, len, aad, aad_len, 1373 tag, AES_BLOCK_SIZE, mode); 1374 } 1375 1376 int rockchip_crypto_ae(struct udevice *dev, cipher_context *ctx, 1377 const u8 *in, u32 len, const u8 *aad, u32 aad_len, 1378 u8 *out, u8 *tag) 1379 1380 { 1381 int ret = 0; 1382 1383 rk_crypto_enable_clk(dev); 1384 1385 ret = rk_crypto_ae(dev, ctx->algo, ctx->mode, ctx->key, ctx->key_len, 1386 ctx->iv, ctx->iv_len, in, len, 1387 aad, aad_len, out, tag); 1388 1389 rk_crypto_disable_clk(dev); 1390 1391 return ret; 1392 } 1393 1394 #endif 1395 1396 #if CONFIG_IS_ENABLED(ROCKCHIP_RSA) 1397 static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, 1398 u8 *sign, u8 *output) 1399 { 1400 struct mpa_num *mpa_m = NULL, *mpa_e = NULL, *mpa_n = NULL; 1401 struct mpa_num *mpa_c = NULL, *mpa_result = NULL; 1402 u32 n_bits, n_words; 1403 int ret; 1404 1405 if (!ctx) 1406 return -EINVAL; 1407 1408 if (ctx->algo != CRYPTO_RSA512 && 1409 ctx->algo != CRYPTO_RSA1024 && 1410 ctx->algo != CRYPTO_RSA2048 && 1411 ctx->algo != CRYPTO_RSA3072 && 1412 ctx->algo != CRYPTO_RSA4096) 1413 return -EINVAL; 1414 1415 n_bits = crypto_algo_nbits(ctx->algo); 1416 n_words = BITS2WORD(n_bits); 1417 1418 ret = rk_mpa_alloc(&mpa_m, sign, n_words); 1419 if (ret) 1420 goto exit; 1421 1422 ret = rk_mpa_alloc(&mpa_e, ctx->e, n_words); 1423 if (ret) 1424 goto exit; 1425 1426 ret = rk_mpa_alloc(&mpa_n, ctx->n, n_words); 1427 if (ret) 1428 goto exit; 1429 1430 if (ctx->c) { 1431 ret = rk_mpa_alloc(&mpa_c, ctx->c, n_words); 1432 if (ret) 1433 goto exit; 1434 } 1435 1436 ret = rk_mpa_alloc(&mpa_result, NULL, n_words); 1437 if (ret) 1438 goto exit; 1439 1440 rk_crypto_enable_clk(dev); 1441 ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result); 1442 if (!ret) 1443 memcpy(output, mpa_result->d, BITS2BYTE(n_bits)); 1444 rk_crypto_disable_clk(dev); 1445 1446 exit: 1447 rk_mpa_free(&mpa_m); 1448 rk_mpa_free(&mpa_e); 1449 rk_mpa_free(&mpa_n); 1450 rk_mpa_free(&mpa_c); 1451 rk_mpa_free(&mpa_result); 1452 1453 return ret; 1454 } 1455 #endif 1456 1457 #if CONFIG_IS_ENABLED(ROCKCHIP_EC) 1458 static int rockchip_crypto_ec_verify(struct udevice *dev, ec_key *ctx, 1459 u8 *hash, u32 hash_len, u8 *sign) 1460 { 1461 struct mpa_num *bn_sign = NULL; 1462 struct rk_ecp_point point_P, point_sign; 1463 u32 n_bits, n_words; 1464 int ret; 1465 1466 if (!ctx) 1467 return -EINVAL; 1468 1469 if (ctx->algo != CRYPTO_SM2 && 1470 ctx->algo != CRYPTO_ECC_192R1 && 1471 ctx->algo != CRYPTO_ECC_224R1 && 1472 ctx->algo != CRYPTO_ECC_256R1) 1473 return -EINVAL; 1474 1475 n_bits = crypto_algo_nbits(ctx->algo); 1476 n_words = BITS2WORD(n_bits); 1477 1478 ret = rk_mpa_alloc(&bn_sign, sign, n_words); 1479 if (ret) 1480 goto exit; 1481 1482 ret = rk_mpa_alloc(&point_P.x, ctx->x, n_words); 1483 ret |= rk_mpa_alloc(&point_P.y, ctx->y, n_words); 1484 if (ret) 1485 goto exit; 1486 1487 ret = rk_mpa_alloc(&point_sign.x, sign, n_words); 1488 ret |= rk_mpa_alloc(&point_sign.y, sign + WORD2BYTE(n_words), n_words); 1489 if (ret) 1490 goto exit; 1491 1492 rk_crypto_enable_clk(dev); 1493 ret = rockchip_ecc_verify(ctx->algo, hash, hash_len, &point_P, &point_sign); 1494 rk_crypto_disable_clk(dev); 1495 exit: 1496 rk_mpa_free(&bn_sign); 1497 rk_mpa_free(&point_P.x); 1498 rk_mpa_free(&point_P.y); 1499 rk_mpa_free(&point_sign.x); 1500 rk_mpa_free(&point_sign.y); 1501 1502 return ret; 1503 } 1504 #endif 1505 1506 static const struct dm_crypto_ops rockchip_crypto_ops = { 1507 .capability = rockchip_crypto_capability, 1508 .sha_init = rockchip_crypto_sha_init, 1509 .sha_update = rockchip_crypto_sha_update, 1510 .sha_final = rockchip_crypto_sha_final, 1511 #if CONFIG_IS_ENABLED(ROCKCHIP_RSA) 1512 .rsa_verify = rockchip_crypto_rsa_verify, 1513 #endif 1514 #if CONFIG_IS_ENABLED(ROCKCHIP_EC) 1515 .ec_verify = rockchip_crypto_ec_verify, 1516 #endif 1517 #if CONFIG_IS_ENABLED(ROCKCHIP_HMAC) 1518 .hmac_init = rockchip_crypto_hmac_init, 1519 .hmac_update = rockchip_crypto_hmac_update, 1520 .hmac_final = rockchip_crypto_hmac_final, 1521 #endif 1522 #if CONFIG_IS_ENABLED(ROCKCHIP_CIPHER) 1523 .cipher_crypt = rockchip_crypto_cipher, 1524 .cipher_mac = rockchip_crypto_mac, 1525 .cipher_ae = rockchip_crypto_ae, 1526 #endif 1527 }; 1528 1529 /* 1530 * Only use "clocks" to parse crypto clock id and use rockchip_get_clk(). 1531 * Because we always add crypto node in U-Boot dts, when kernel dtb enabled : 1532 * 1533 * 1. There is cru phandle mismatch between U-Boot and kernel dtb; 1534 * 2. CONFIG_OF_SPL_REMOVE_PROPS removes clock property; 1535 */ 1536 static int rockchip_crypto_ofdata_to_platdata(struct udevice *dev) 1537 { 1538 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 1539 int len, ret = -EINVAL; 1540 1541 memset(priv, 0x00, sizeof(*priv)); 1542 1543 priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev); 1544 if (priv->reg == FDT_ADDR_T_NONE) 1545 return -EINVAL; 1546 1547 crypto_base = priv->reg; 1548 1549 /* if there is no clocks in dts, just skip it */ 1550 if (!dev_read_prop(dev, "clocks", &len)) { 1551 printf("Can't find \"clocks\" property\n"); 1552 return 0; 1553 } 1554 1555 memset(priv, 0x00, sizeof(*priv)); 1556 priv->clocks = malloc(len); 1557 if (!priv->clocks) 1558 return -ENOMEM; 1559 1560 priv->nclocks = len / (2 * sizeof(u32)); 1561 if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks, 1562 priv->nclocks)) { 1563 printf("Can't read \"clocks\" property\n"); 1564 ret = -EINVAL; 1565 goto exit; 1566 } 1567 1568 if (dev_read_prop(dev, "clock-frequency", &len)) { 1569 priv->frequencies = malloc(len); 1570 if (!priv->frequencies) { 1571 ret = -ENOMEM; 1572 goto exit; 1573 } 1574 priv->freq_nclocks = len / sizeof(u32); 1575 if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies, 1576 priv->freq_nclocks)) { 1577 printf("Can't read \"clock-frequency\" property\n"); 1578 ret = -EINVAL; 1579 goto exit; 1580 } 1581 } 1582 1583 return 0; 1584 exit: 1585 if (priv->clocks) 1586 free(priv->clocks); 1587 1588 if (priv->frequencies) 1589 free(priv->frequencies); 1590 1591 return ret; 1592 } 1593 1594 static int rk_crypto_set_clk(struct udevice *dev) 1595 { 1596 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 1597 struct clk clk; 1598 int i, ret; 1599 1600 /* use standard "assigned-clock-rates" props */ 1601 if (dev_read_size(dev, "assigned-clock-rates") > 0) 1602 return clk_set_defaults(dev); 1603 1604 /* use "clock-frequency" props */ 1605 if (priv->freq_nclocks == 0) 1606 return 0; 1607 1608 for (i = 0; i < priv->freq_nclocks; i++) { 1609 ret = clk_get_by_index(dev, i, &clk); 1610 if (ret < 0) { 1611 printf("Failed to get clk index %d, ret=%d\n", i, ret); 1612 return ret; 1613 } 1614 ret = clk_set_rate(&clk, priv->frequencies[i]); 1615 if (ret < 0) { 1616 printf("%s: Failed to set clk(%ld): ret=%d\n", 1617 __func__, clk.id, ret); 1618 return ret; 1619 } 1620 } 1621 1622 return 0; 1623 } 1624 1625 static int rockchip_crypto_probe(struct udevice *dev) 1626 { 1627 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 1628 struct rk_crypto_soc_data *sdata; 1629 int ret = 0; 1630 1631 sdata = (struct rk_crypto_soc_data *)dev_get_driver_data(dev); 1632 1633 if (sdata->dynamic_cap) 1634 sdata->capability = sdata->dynamic_cap(); 1635 1636 priv->soc_data = sdata; 1637 1638 priv->hw_ctx = memalign(LLI_ADDR_ALIGN_SIZE, 1639 sizeof(struct rk_hash_ctx)); 1640 if (!priv->hw_ctx) 1641 return -ENOMEM; 1642 1643 ret = rk_crypto_set_clk(dev); 1644 if (ret) 1645 return ret; 1646 1647 rk_crypto_enable_clk(dev); 1648 1649 hw_crypto_reset(); 1650 1651 rk_crypto_disable_clk(dev); 1652 1653 return 0; 1654 } 1655 1656 static const struct rk_crypto_soc_data soc_data_base = { 1657 .capability = CRYPTO_MD5 | 1658 CRYPTO_SHA1 | 1659 CRYPTO_SHA256 | 1660 CRYPTO_SHA512 | 1661 CRYPTO_HMAC_MD5 | 1662 CRYPTO_HMAC_SHA1 | 1663 CRYPTO_HMAC_SHA256 | 1664 CRYPTO_HMAC_SHA512 | 1665 CRYPTO_RSA512 | 1666 CRYPTO_RSA1024 | 1667 CRYPTO_RSA2048 | 1668 CRYPTO_RSA3072 | 1669 CRYPTO_RSA4096 | 1670 CRYPTO_DES | 1671 CRYPTO_AES, 1672 }; 1673 1674 static const struct rk_crypto_soc_data soc_data_base_sm = { 1675 .capability = CRYPTO_MD5 | 1676 CRYPTO_SHA1 | 1677 CRYPTO_SHA256 | 1678 CRYPTO_SHA512 | 1679 CRYPTO_SM3 | 1680 CRYPTO_HMAC_MD5 | 1681 CRYPTO_HMAC_SHA1 | 1682 CRYPTO_HMAC_SHA256 | 1683 CRYPTO_HMAC_SHA512 | 1684 CRYPTO_HMAC_SM3 | 1685 CRYPTO_RSA512 | 1686 CRYPTO_RSA1024 | 1687 CRYPTO_RSA2048 | 1688 CRYPTO_RSA3072 | 1689 CRYPTO_RSA4096 | 1690 CRYPTO_DES | 1691 CRYPTO_AES | 1692 CRYPTO_SM4, 1693 }; 1694 1695 static const struct rk_crypto_soc_data soc_data_rk1808 = { 1696 .capability = CRYPTO_MD5 | 1697 CRYPTO_SHA1 | 1698 CRYPTO_SHA256 | 1699 CRYPTO_HMAC_MD5 | 1700 CRYPTO_HMAC_SHA1 | 1701 CRYPTO_HMAC_SHA256 | 1702 CRYPTO_RSA512 | 1703 CRYPTO_RSA1024 | 1704 CRYPTO_RSA2048 | 1705 CRYPTO_RSA3072 | 1706 CRYPTO_RSA4096, 1707 }; 1708 1709 static const struct rk_crypto_soc_data soc_data_cryptov3 = { 1710 .capability = 0, 1711 .dynamic_cap = crypto_v3_dynamic_cap, 1712 }; 1713 1714 static const struct udevice_id rockchip_crypto_ids[] = { 1715 { 1716 .compatible = "rockchip,px30-crypto", 1717 .data = (ulong)&soc_data_base 1718 }, 1719 { 1720 .compatible = "rockchip,rk1808-crypto", 1721 .data = (ulong)&soc_data_rk1808 1722 }, 1723 { 1724 .compatible = "rockchip,rk3308-crypto", 1725 .data = (ulong)&soc_data_base 1726 }, 1727 { 1728 .compatible = "rockchip,rv1126-crypto", 1729 .data = (ulong)&soc_data_base_sm 1730 }, 1731 { 1732 .compatible = "rockchip,rk3568-crypto", 1733 .data = (ulong)&soc_data_base_sm 1734 }, 1735 { 1736 .compatible = "rockchip,rk3588-crypto", 1737 .data = (ulong)&soc_data_base_sm 1738 }, 1739 { 1740 .compatible = "rockchip,crypto-v3", 1741 .data = (ulong)&soc_data_cryptov3 1742 }, 1743 { 1744 .compatible = "rockchip,crypto-v4", 1745 .data = (ulong)&soc_data_cryptov3 /* reuse crypto v3 config */ 1746 }, 1747 { } 1748 }; 1749 1750 U_BOOT_DRIVER(rockchip_crypto_v2) = { 1751 .name = "rockchip_crypto_v2", 1752 .id = UCLASS_CRYPTO, 1753 .of_match = rockchip_crypto_ids, 1754 .ops = &rockchip_crypto_ops, 1755 .probe = rockchip_crypto_probe, 1756 .ofdata_to_platdata = rockchip_crypto_ofdata_to_platdata, 1757 .priv_auto_alloc_size = sizeof(struct rockchip_crypto_priv), 1758 }; 1759