1*31f8f6ebSJoseph Chen/* 2*31f8f6ebSJoseph Chen * Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd 3*31f8f6ebSJoseph Chen * SPDX-License-Identifier: GPL-2.0 4*31f8f6ebSJoseph Chen */ 5*31f8f6ebSJoseph Chen 6*31f8f6ebSJoseph Chen/dts-v1/; 7*31f8f6ebSJoseph Chen/ { 8*31f8f6ebSJoseph Chen description = "FIT source file for rockchip AMP"; 9*31f8f6ebSJoseph Chen #address-cells = <1>; 10*31f8f6ebSJoseph Chen 11*31f8f6ebSJoseph Chen images { 12*31f8f6ebSJoseph Chen 13*31f8f6ebSJoseph Chen amp0 { 14*31f8f6ebSJoseph Chen description = "bare-mental-core0"; 15*31f8f6ebSJoseph Chen data = /incbin/("../../hal0.bin"); 16*31f8f6ebSJoseph Chen type = "firmware"; 17*31f8f6ebSJoseph Chen compression = "none"; 18*31f8f6ebSJoseph Chen arch = "arm"; // "arm64" or "arm" 19*31f8f6ebSJoseph Chen cpu = <0x000>; // mpidr 20*31f8f6ebSJoseph Chen thumb = <0>; // 0: arm or thumb2; 1: thumb 21*31f8f6ebSJoseph Chen hyp = <0>; // 0: el1/svc; 1: el2/hyp 22*31f8f6ebSJoseph Chen load = <0xa00000>; 23*31f8f6ebSJoseph Chen udelay = <500000>; 24*31f8f6ebSJoseph Chen hash { 25*31f8f6ebSJoseph Chen algo = "sha256"; 26*31f8f6ebSJoseph Chen }; 27*31f8f6ebSJoseph Chen }; 28*31f8f6ebSJoseph Chen 29*31f8f6ebSJoseph Chen amp1 { 30*31f8f6ebSJoseph Chen description = "bare-mental-core1"; 31*31f8f6ebSJoseph Chen data = /incbin/("../../hal1.bin"); 32*31f8f6ebSJoseph Chen type = "firmware"; 33*31f8f6ebSJoseph Chen compression = "none"; 34*31f8f6ebSJoseph Chen arch = "arm"; 35*31f8f6ebSJoseph Chen cpu = <0x100>; 36*31f8f6ebSJoseph Chen thumb = <0>; 37*31f8f6ebSJoseph Chen hyp = <0>; 38*31f8f6ebSJoseph Chen load = <0xb00000>; 39*31f8f6ebSJoseph Chen udelay = <500000>; 40*31f8f6ebSJoseph Chen hash { 41*31f8f6ebSJoseph Chen algo = "sha256"; 42*31f8f6ebSJoseph Chen }; 43*31f8f6ebSJoseph Chen }; 44*31f8f6ebSJoseph Chen 45*31f8f6ebSJoseph Chen amp2 { 46*31f8f6ebSJoseph Chen description = "bare-mental-core2"; 47*31f8f6ebSJoseph Chen data = /incbin/("../../hal2.bin"); 48*31f8f6ebSJoseph Chen type = "firmware"; 49*31f8f6ebSJoseph Chen compression = "none"; 50*31f8f6ebSJoseph Chen arch = "arm"; 51*31f8f6ebSJoseph Chen cpu = <0x200>; 52*31f8f6ebSJoseph Chen thumb = <0>; 53*31f8f6ebSJoseph Chen hyp = <0>; 54*31f8f6ebSJoseph Chen load = <0xc00000>; 55*31f8f6ebSJoseph Chen udelay = <500000>; 56*31f8f6ebSJoseph Chen hash { 57*31f8f6ebSJoseph Chen algo = "sha256"; 58*31f8f6ebSJoseph Chen }; 59*31f8f6ebSJoseph Chen }; 60*31f8f6ebSJoseph Chen 61*31f8f6ebSJoseph Chen amp3 { 62*31f8f6ebSJoseph Chen description = "bare-mental-core3"; 63*31f8f6ebSJoseph Chen data = /incbin/("../../hal3.bin"); 64*31f8f6ebSJoseph Chen type = "firmware"; 65*31f8f6ebSJoseph Chen compression = "none"; 66*31f8f6ebSJoseph Chen arch = "arm"; 67*31f8f6ebSJoseph Chen cpu = <0x300>; 68*31f8f6ebSJoseph Chen thumb = <0>; 69*31f8f6ebSJoseph Chen hyp = <0>; 70*31f8f6ebSJoseph Chen load = <0xd00000>; 71*31f8f6ebSJoseph Chen udelay = <500000>; 72*31f8f6ebSJoseph Chen hash { 73*31f8f6ebSJoseph Chen algo = "sha256"; 74*31f8f6ebSJoseph Chen }; 75*31f8f6ebSJoseph Chen }; 76*31f8f6ebSJoseph Chen }; 77*31f8f6ebSJoseph Chen 78*31f8f6ebSJoseph Chen configurations { 79*31f8f6ebSJoseph Chen default = "conf"; 80*31f8f6ebSJoseph Chen conf { 81*31f8f6ebSJoseph Chen description = "Rockchip AMP images"; 82*31f8f6ebSJoseph Chen rollback-index = <0x0>; 83*31f8f6ebSJoseph Chen loadables = "amp0", "amp1", "amp2", "amp3"; 84*31f8f6ebSJoseph Chen 85*31f8f6ebSJoseph Chen signature { 86*31f8f6ebSJoseph Chen algo = "sha256,rsa2048"; 87*31f8f6ebSJoseph Chen padding = "pss"; 88*31f8f6ebSJoseph Chen key-name-hint = "dev"; 89*31f8f6ebSJoseph Chen sign-images = "loadables"; 90*31f8f6ebSJoseph Chen }; 91*31f8f6ebSJoseph Chen }; 92*31f8f6ebSJoseph Chen }; 93*31f8f6ebSJoseph Chen}; 94