xref: /rk3399_rockchip-uboot/drivers/clk/clk-uclass.c (revision 2ae83ee4a9c4733d431bfff3e674aaf2adb6b751)
1 /*
2  * Copyright (C) 2015 Google, Inc
3  * Written by Simon Glass <sjg@chromium.org>
4  * Copyright (c) 2016, NVIDIA CORPORATION.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #include <common.h>
10 #include <clk.h>
11 #include <clk-uclass.h>
12 #include <dm.h>
13 #include <dt-structs.h>
14 #include <errno.h>
15 
16 static inline const struct clk_ops *clk_dev_ops(struct udevice *dev)
17 {
18 	return (const struct clk_ops *)dev->driver->ops;
19 }
20 
21 #if CONFIG_IS_ENABLED(OF_CONTROL)
22 # if CONFIG_IS_ENABLED(OF_PLATDATA)
23 int clk_get_by_index_platdata(struct udevice *dev, int index,
24 			      struct phandle_1_arg *cells, struct clk *clk)
25 {
26 	int ret;
27 
28 	if (index != 0)
29 		return -ENOSYS;
30 	ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev);
31 	if (ret)
32 		return ret;
33 	clk->id = cells[0].arg[0];
34 
35 	return 0;
36 }
37 # else
38 static int clk_of_xlate_default(struct clk *clk,
39 				struct ofnode_phandle_args *args)
40 {
41 	debug("%s(clk=%p)\n", __func__, clk);
42 
43 	if (args->args_count > 1) {
44 		debug("Invaild args_count: %d\n", args->args_count);
45 		return -EINVAL;
46 	}
47 
48 	if (args->args_count)
49 		clk->id = args->args[0];
50 	else
51 		clk->id = 0;
52 
53 	return 0;
54 }
55 
56 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
57 				   int index, struct clk *clk)
58 {
59 	int ret;
60 	struct ofnode_phandle_args args;
61 	struct udevice *dev_clk;
62 	const struct clk_ops *ops;
63 
64 	debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
65 
66 	assert(clk);
67 	clk->dev = NULL;
68 
69 	ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
70 					 index, &args);
71 	if (ret) {
72 		debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
73 		      __func__, ret);
74 		return ret;
75 	}
76 
77 	ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
78 	if (ret) {
79 		debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
80 		      __func__, ret);
81 		return ret;
82 	}
83 
84 	clk->dev = dev_clk;
85 
86 	ops = clk_dev_ops(dev_clk);
87 
88 	if (ops->of_xlate)
89 		ret = ops->of_xlate(clk, &args);
90 	else
91 		ret = clk_of_xlate_default(clk, &args);
92 	if (ret) {
93 		debug("of_xlate() failed: %d\n", ret);
94 		return ret;
95 	}
96 
97 	return clk_request(dev_clk, clk);
98 }
99 
100 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
101 {
102 	return clk_get_by_indexed_prop(dev, "clocks", index, clk);
103 }
104 # endif /* OF_PLATDATA */
105 
106 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
107 {
108 	int index;
109 
110 	debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
111 	clk->dev = NULL;
112 
113 	index = dev_read_stringlist_search(dev, "clock-names", name);
114 	if (index < 0) {
115 		debug("fdt_stringlist_search() failed: %d\n", index);
116 		return index;
117 	}
118 
119 	return clk_get_by_index(dev, index, clk);
120 }
121 
122 int clk_release_all(struct clk *clk, int count)
123 {
124 	int i, ret;
125 
126 	for (i = 0; i < count; i++) {
127 		debug("%s(clk[%d]=%p)\n", __func__, i, &clk[i]);
128 
129 		/* check if clock has been previously requested */
130 		if (!clk[i].dev)
131 			continue;
132 
133 		ret = clk_disable(&clk[i]);
134 		if (ret && ret != -ENOSYS)
135 			return ret;
136 
137 		ret = clk_free(&clk[i]);
138 		if (ret && ret != -ENOSYS)
139 			return ret;
140 	}
141 
142 	return 0;
143 }
144 
145 #endif /* OF_CONTROL */
146 
147 int clk_request(struct udevice *dev, struct clk *clk)
148 {
149 	const struct clk_ops *ops = clk_dev_ops(dev);
150 
151 	debug("%s(dev=%p, clk=%p)\n", __func__, dev, clk);
152 
153 	clk->dev = dev;
154 
155 	if (!ops->request)
156 		return 0;
157 
158 	return ops->request(clk);
159 }
160 
161 int clk_free(struct clk *clk)
162 {
163 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
164 
165 	debug("%s(clk=%p)\n", __func__, clk);
166 
167 	if (!ops->free)
168 		return 0;
169 
170 	return ops->free(clk);
171 }
172 
173 ulong clk_get_rate(struct clk *clk)
174 {
175 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
176 
177 	debug("%s(clk=%p)\n", __func__, clk);
178 
179 	if (!ops->get_rate)
180 		return -ENOSYS;
181 
182 	return ops->get_rate(clk);
183 }
184 
185 ulong clk_set_rate(struct clk *clk, ulong rate)
186 {
187 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
188 
189 	debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate);
190 
191 	if (!ops->set_rate)
192 		return -ENOSYS;
193 
194 	return ops->set_rate(clk, rate);
195 }
196 
197 int clk_get_phase(struct clk *clk)
198 {
199 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
200 
201 	if (!ops->get_phase)
202 		return -ENOSYS;
203 
204 	return ops->get_phase(clk);
205 }
206 
207 int clk_set_phase(struct clk *clk, int degrees)
208 {
209 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
210 
211 	if (!ops->set_phase)
212 		return -ENOSYS;
213 
214 	return ops->set_phase(clk, degrees);
215 }
216 
217 int clk_set_parent(struct clk *clk, struct clk *parent)
218 {
219 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
220 
221 	debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
222 
223 	if (!ops->set_parent)
224 		return -ENOSYS;
225 
226 	return ops->set_parent(clk, parent);
227 }
228 
229 int clk_enable(struct clk *clk)
230 {
231 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
232 
233 	debug("%s(clk=%p)\n", __func__, clk);
234 
235 	if (!ops->enable)
236 		return -ENOSYS;
237 
238 	return ops->enable(clk);
239 }
240 
241 int clk_disable(struct clk *clk)
242 {
243 	const struct clk_ops *ops = clk_dev_ops(clk->dev);
244 
245 	debug("%s(clk=%p)\n", __func__, clk);
246 
247 	if (!ops->disable)
248 		return -ENOSYS;
249 
250 	return ops->disable(clk);
251 }
252 
253 UCLASS_DRIVER(clk) = {
254 	.id		= UCLASS_CLK,
255 	.name		= "clk",
256 };
257