xref: /rk3399_rockchip-uboot/drivers/clk/at91/clk-slow.c (revision 9d922450aa9944ecf8c249c892078cda80f40e02)
19e5935c0SWenyou Yang /*
29e5935c0SWenyou Yang  * Copyright (C) 2016 Atmel Corporation
39e5935c0SWenyou Yang  *               Wenyou.Yang <wenyou.yang@atmel.com>
49e5935c0SWenyou Yang  *
59e5935c0SWenyou Yang  * SPDX-License-Identifier:	GPL-2.0+
69e5935c0SWenyou Yang  */
79e5935c0SWenyou Yang 
89e5935c0SWenyou Yang #include <common.h>
99e5935c0SWenyou Yang #include <clk-uclass.h>
10*9d922450SSimon Glass #include <dm.h>
119e5935c0SWenyou Yang 
at91_slow_clk_enable(struct clk * clk)129e5935c0SWenyou Yang static int at91_slow_clk_enable(struct clk *clk)
139e5935c0SWenyou Yang {
149e5935c0SWenyou Yang 	return 0;
159e5935c0SWenyou Yang }
169e5935c0SWenyou Yang 
at91_slow_clk_get_rate(struct clk * clk)179e5935c0SWenyou Yang static ulong at91_slow_clk_get_rate(struct clk *clk)
189e5935c0SWenyou Yang {
199e5935c0SWenyou Yang 	return CONFIG_SYS_AT91_SLOW_CLOCK;
209e5935c0SWenyou Yang }
219e5935c0SWenyou Yang 
229e5935c0SWenyou Yang static struct clk_ops at91_slow_clk_ops = {
239e5935c0SWenyou Yang 	.enable = at91_slow_clk_enable,
249e5935c0SWenyou Yang 	.get_rate = at91_slow_clk_get_rate,
259e5935c0SWenyou Yang };
269e5935c0SWenyou Yang 
279e5935c0SWenyou Yang static const struct udevice_id at91_slow_clk_match[] = {
289e5935c0SWenyou Yang 	{ .compatible = "atmel,at91sam9x5-clk-slow" },
299e5935c0SWenyou Yang 	{}
309e5935c0SWenyou Yang };
319e5935c0SWenyou Yang 
329e5935c0SWenyou Yang U_BOOT_DRIVER(at91_slow_clk) = {
339e5935c0SWenyou Yang 	.name = "at91-slow-clk",
349e5935c0SWenyou Yang 	.id = UCLASS_CLK,
359e5935c0SWenyou Yang 	.of_match = at91_slow_clk_match,
369e5935c0SWenyou Yang 	.ops = &at91_slow_clk_ops,
379e5935c0SWenyou Yang };
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