1 /* 2 * Copyright (c) 2004 Picture Elements, Inc. 3 * Stephen Williams (XXXXXXXXXXXXXXXX) 4 * 5 * This source code is free software; you can redistribute it 6 * and/or modify it in source code form under the terms of the GNU 7 * General Public License as published by the Free Software 8 * Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA 19 */ 20 21 /* 22 * The Xilinx SystemACE chip support is activated by defining 23 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE 24 * to set the base address of the device. This code currently 25 * assumes that the chip is connected via a byte-wide bus. 26 * 27 * The CONFIG_SYSTEMACE also adds to fat support the device class 28 * "ace" that allows the user to execute "fatls ace 0" and the 29 * like. This works by making the systemace_get_dev function 30 * available to cmd_fat.c:get_dev and filling in a block device 31 * description that has all the bits needed for FAT support to 32 * read sectors. 33 * 34 * According to Xilinx technical support, before accessing the 35 * SystemACE CF you need to set the following control bits: 36 * FORCECFGMODE : 1 37 * CFGMODE : 0 38 * CFGSTART : 0 39 */ 40 41 #include <common.h> 42 #include <command.h> 43 #include <systemace.h> 44 #include <part.h> 45 #include <asm/io.h> 46 47 /* 48 * The ace_readw and writew functions read/write 16bit words, but the 49 * offset value is the BYTE offset as most used in the Xilinx 50 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined 51 * to be the base address for the chip, usually in the local 52 * peripheral bus. 53 */ 54 55 static u32 base = CONFIG_SYS_SYSTEMACE_BASE; 56 static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; 57 58 static void ace_writew(u16 val, unsigned off) 59 { 60 if (width == 8) { 61 #if !defined(__BIG_ENDIAN) 62 writeb(val >> 8, base + off); 63 writeb(val, base + off + 1); 64 #else 65 writeb(val, base + off); 66 writeb(val >> 8, base + off + 1); 67 #endif 68 } 69 out16(base + off, val); 70 } 71 72 static u16 ace_readw(unsigned off) 73 { 74 if (width == 8) { 75 #if !defined(__BIG_ENDIAN) 76 return (readb(base + off) << 8) | readb(base + off + 1); 77 #else 78 return readb(base + off) | (readb(base + off + 1) << 8); 79 #endif 80 } 81 82 return in16(base + off); 83 } 84 85 static unsigned long systemace_read(int dev, unsigned long start, 86 unsigned long blkcnt, void *buffer); 87 88 static block_dev_desc_t systemace_dev = { 0 }; 89 90 static int get_cf_lock(void) 91 { 92 int retry = 10; 93 94 /* CONTROLREG = LOCKREG */ 95 unsigned val = ace_readw(0x18); 96 val |= 0x0002; 97 ace_writew((val & 0xffff), 0x18); 98 99 /* Wait for MPULOCK in STATUSREG[15:0] */ 100 while (!(ace_readw(0x04) & 0x0002)) { 101 102 if (retry < 0) 103 return -1; 104 105 udelay(100000); 106 retry -= 1; 107 } 108 109 return 0; 110 } 111 112 static void release_cf_lock(void) 113 { 114 unsigned val = ace_readw(0x18); 115 val &= ~(0x0002); 116 ace_writew((val & 0xffff), 0x18); 117 } 118 119 #ifdef CONFIG_PARTITIONS 120 block_dev_desc_t *systemace_get_dev(int dev) 121 { 122 /* The first time through this, the systemace_dev object is 123 not yet initialized. In that case, fill it in. */ 124 if (systemace_dev.blksz == 0) { 125 systemace_dev.if_type = IF_TYPE_UNKNOWN; 126 systemace_dev.dev = 0; 127 systemace_dev.part_type = PART_TYPE_UNKNOWN; 128 systemace_dev.type = DEV_TYPE_HARDDISK; 129 systemace_dev.blksz = 512; 130 systemace_dev.removable = 1; 131 systemace_dev.block_read = systemace_read; 132 133 /* 134 * Ensure the correct bus mode (8/16 bits) gets enabled 135 */ 136 ace_writew(width == 8 ? 0 : 0x0001, 0); 137 138 init_part(&systemace_dev); 139 140 } 141 142 return &systemace_dev; 143 } 144 #endif 145 146 /* 147 * This function is called (by dereferencing the block_read pointer in 148 * the dev_desc) to read blocks of data. The return value is the 149 * number of blocks read. A zero return indicates an error. 150 */ 151 static unsigned long systemace_read(int dev, unsigned long start, 152 unsigned long blkcnt, void *buffer) 153 { 154 int retry; 155 unsigned blk_countdown; 156 unsigned char *dp = buffer; 157 unsigned val; 158 159 if (get_cf_lock() < 0) { 160 unsigned status = ace_readw(0x04); 161 162 /* If CFDETECT is false, card is missing. */ 163 if (!(status & 0x0010)) { 164 printf("** CompactFlash card not present. **\n"); 165 return 0; 166 } 167 168 printf("**** ACE locked away from me (STATUSREG=%04x)\n", 169 status); 170 return 0; 171 } 172 #ifdef DEBUG_SYSTEMACE 173 printf("... systemace read %lu sectors at %lu\n", blkcnt, start); 174 #endif 175 176 retry = 2000; 177 for (;;) { 178 val = ace_readw(0x04); 179 180 /* If CFDETECT is false, card is missing. */ 181 if (!(val & 0x0010)) { 182 printf("**** ACE CompactFlash not found.\n"); 183 release_cf_lock(); 184 return 0; 185 } 186 187 /* If RDYFORCMD, then we are ready to go. */ 188 if (val & 0x0100) 189 break; 190 191 if (retry < 0) { 192 printf("**** SystemACE not ready.\n"); 193 release_cf_lock(); 194 return 0; 195 } 196 197 udelay(1000); 198 retry -= 1; 199 } 200 201 /* The SystemACE can only transfer 256 sectors at a time, so 202 limit the current chunk of sectors. The blk_countdown 203 variable is the number of sectors left to transfer. */ 204 205 blk_countdown = blkcnt; 206 while (blk_countdown > 0) { 207 unsigned trans = blk_countdown; 208 209 if (trans > 256) 210 trans = 256; 211 212 #ifdef DEBUG_SYSTEMACE 213 printf("... transfer %lu sector in a chunk\n", trans); 214 #endif 215 /* Write LBA block address */ 216 ace_writew((start >> 0) & 0xffff, 0x10); 217 ace_writew((start >> 16) & 0x0fff, 0x12); 218 219 /* NOTE: in the Write Sector count below, a count of 0 220 causes a transfer of 256, so &0xff gives the right 221 value for whatever transfer count we want. */ 222 223 /* Write sector count | ReadMemCardData. */ 224 ace_writew((trans & 0xff) | 0x0300, 0x14); 225 226 /* 227 * For FPGA configuration via SystemACE is reset unacceptable 228 * CFGDONE bit in STATUSREG is not set to 1. 229 */ 230 #ifndef SYSTEMACE_CONFIG_FPGA 231 /* Reset the configruation controller */ 232 val = ace_readw(0x18); 233 val |= 0x0080; 234 ace_writew(val, 0x18); 235 #endif 236 237 retry = trans * 16; 238 while (retry > 0) { 239 int idx; 240 241 /* Wait for buffer to become ready. */ 242 while (!(ace_readw(0x04) & 0x0020)) { 243 udelay(100); 244 } 245 246 /* Read 16 words of 2bytes from the sector buffer. */ 247 for (idx = 0; idx < 16; idx += 1) { 248 unsigned short val = ace_readw(0x40); 249 *dp++ = val & 0xff; 250 *dp++ = (val >> 8) & 0xff; 251 } 252 253 retry -= 1; 254 } 255 256 /* Clear the configruation controller reset */ 257 val = ace_readw(0x18); 258 val &= ~0x0080; 259 ace_writew(val, 0x18); 260 261 /* Count the blocks we transfer this time. */ 262 start += trans; 263 blk_countdown -= trans; 264 } 265 266 release_cf_lock(); 267 268 return blkcnt; 269 } 270