1 /* 2 * Copyright (c) 2004 Picture Elements, Inc. 3 * Stephen Williams (XXXXXXXXXXXXXXXX) 4 * 5 * This source code is free software; you can redistribute it 6 * and/or modify it in source code form under the terms of the GNU 7 * General Public License as published by the Free Software 8 * Foundation; either version 2 of the License, or (at your option) 9 * any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA 19 */ 20 21 /* 22 * The Xilinx SystemACE chip support is activated by defining 23 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE 24 * to set the base address of the device. This code currently 25 * assumes that the chip is connected via a byte-wide bus. 26 * 27 * The CONFIG_SYSTEMACE also adds to fat support the device class 28 * "ace" that allows the user to execute "fatls ace 0" and the 29 * like. This works by making the systemace_get_dev function 30 * available to cmd_fat.c:get_dev and filling in a block device 31 * description that has all the bits needed for FAT support to 32 * read sectors. 33 * 34 * According to Xilinx technical support, before accessing the 35 * SystemACE CF you need to set the following control bits: 36 * FORCECFGMODE : 1 37 * CFGMODE : 0 38 * CFGSTART : 0 39 */ 40 41 #include <common.h> 42 #include <command.h> 43 #include <systemace.h> 44 #include <part.h> 45 #include <asm/io.h> 46 47 /* 48 * The ace_readw and writew functions read/write 16bit words, but the 49 * offset value is the BYTE offset as most used in the Xilinx 50 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined 51 * to be the base address for the chip, usually in the local 52 * peripheral bus. 53 */ 54 #if (CONFIG_SYS_SYSTEMACE_WIDTH == 8) 55 #if !defined(__BIG_ENDIAN) 56 #define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)<<8) | \ 57 (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1))) 58 #define ace_writew(val, off) {writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off); \ 59 writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off+1);} 60 #else 61 #define ace_readw(off) ((readb(CONFIG_SYS_SYSTEMACE_BASE+off)) | \ 62 (readb(CONFIG_SYS_SYSTEMACE_BASE+off+1)<<8)) 63 #define ace_writew(val, off) {writeb(val, CONFIG_SYS_SYSTEMACE_BASE+off); \ 64 writeb(val>>8, CONFIG_SYS_SYSTEMACE_BASE+off+1);} 65 #endif 66 #else 67 #define ace_readw(off) (in16(CONFIG_SYS_SYSTEMACE_BASE+off)) 68 #define ace_writew(val, off) (out16(CONFIG_SYS_SYSTEMACE_BASE+off,val)) 69 #endif 70 71 /* */ 72 73 static unsigned long systemace_read(int dev, unsigned long start, 74 unsigned long blkcnt, void *buffer); 75 76 static block_dev_desc_t systemace_dev = { 0 }; 77 78 static int get_cf_lock(void) 79 { 80 int retry = 10; 81 82 /* CONTROLREG = LOCKREG */ 83 unsigned val = ace_readw(0x18); 84 val |= 0x0002; 85 ace_writew((val & 0xffff), 0x18); 86 87 /* Wait for MPULOCK in STATUSREG[15:0] */ 88 while (!(ace_readw(0x04) & 0x0002)) { 89 90 if (retry < 0) 91 return -1; 92 93 udelay(100000); 94 retry -= 1; 95 } 96 97 return 0; 98 } 99 100 static void release_cf_lock(void) 101 { 102 unsigned val = ace_readw(0x18); 103 val &= ~(0x0002); 104 ace_writew((val & 0xffff), 0x18); 105 } 106 107 #ifdef CONFIG_PARTITIONS 108 block_dev_desc_t *systemace_get_dev(int dev) 109 { 110 /* The first time through this, the systemace_dev object is 111 not yet initialized. In that case, fill it in. */ 112 if (systemace_dev.blksz == 0) { 113 systemace_dev.if_type = IF_TYPE_UNKNOWN; 114 systemace_dev.dev = 0; 115 systemace_dev.part_type = PART_TYPE_UNKNOWN; 116 systemace_dev.type = DEV_TYPE_HARDDISK; 117 systemace_dev.blksz = 512; 118 systemace_dev.removable = 1; 119 systemace_dev.block_read = systemace_read; 120 121 /* 122 * Ensure the correct bus mode (8/16 bits) gets enabled 123 */ 124 ace_writew(CONFIG_SYS_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); 125 126 init_part(&systemace_dev); 127 128 } 129 130 return &systemace_dev; 131 } 132 #endif 133 134 /* 135 * This function is called (by dereferencing the block_read pointer in 136 * the dev_desc) to read blocks of data. The return value is the 137 * number of blocks read. A zero return indicates an error. 138 */ 139 static unsigned long systemace_read(int dev, unsigned long start, 140 unsigned long blkcnt, void *buffer) 141 { 142 int retry; 143 unsigned blk_countdown; 144 unsigned char *dp = buffer; 145 unsigned val; 146 147 if (get_cf_lock() < 0) { 148 unsigned status = ace_readw(0x04); 149 150 /* If CFDETECT is false, card is missing. */ 151 if (!(status & 0x0010)) { 152 printf("** CompactFlash card not present. **\n"); 153 return 0; 154 } 155 156 printf("**** ACE locked away from me (STATUSREG=%04x)\n", 157 status); 158 return 0; 159 } 160 #ifdef DEBUG_SYSTEMACE 161 printf("... systemace read %lu sectors at %lu\n", blkcnt, start); 162 #endif 163 164 retry = 2000; 165 for (;;) { 166 val = ace_readw(0x04); 167 168 /* If CFDETECT is false, card is missing. */ 169 if (!(val & 0x0010)) { 170 printf("**** ACE CompactFlash not found.\n"); 171 release_cf_lock(); 172 return 0; 173 } 174 175 /* If RDYFORCMD, then we are ready to go. */ 176 if (val & 0x0100) 177 break; 178 179 if (retry < 0) { 180 printf("**** SystemACE not ready.\n"); 181 release_cf_lock(); 182 return 0; 183 } 184 185 udelay(1000); 186 retry -= 1; 187 } 188 189 /* The SystemACE can only transfer 256 sectors at a time, so 190 limit the current chunk of sectors. The blk_countdown 191 variable is the number of sectors left to transfer. */ 192 193 blk_countdown = blkcnt; 194 while (blk_countdown > 0) { 195 unsigned trans = blk_countdown; 196 197 if (trans > 256) 198 trans = 256; 199 200 #ifdef DEBUG_SYSTEMACE 201 printf("... transfer %lu sector in a chunk\n", trans); 202 #endif 203 /* Write LBA block address */ 204 ace_writew((start >> 0) & 0xffff, 0x10); 205 ace_writew((start >> 16) & 0x0fff, 0x12); 206 207 /* NOTE: in the Write Sector count below, a count of 0 208 causes a transfer of 256, so &0xff gives the right 209 value for whatever transfer count we want. */ 210 211 /* Write sector count | ReadMemCardData. */ 212 ace_writew((trans & 0xff) | 0x0300, 0x14); 213 214 /* 215 * For FPGA configuration via SystemACE is reset unacceptable 216 * CFGDONE bit in STATUSREG is not set to 1. 217 */ 218 #ifndef SYSTEMACE_CONFIG_FPGA 219 /* Reset the configruation controller */ 220 val = ace_readw(0x18); 221 val |= 0x0080; 222 ace_writew(val, 0x18); 223 #endif 224 225 retry = trans * 16; 226 while (retry > 0) { 227 int idx; 228 229 /* Wait for buffer to become ready. */ 230 while (!(ace_readw(0x04) & 0x0020)) { 231 udelay(100); 232 } 233 234 /* Read 16 words of 2bytes from the sector buffer. */ 235 for (idx = 0; idx < 16; idx += 1) { 236 unsigned short val = ace_readw(0x40); 237 *dp++ = val & 0xff; 238 *dp++ = (val >> 8) & 0xff; 239 } 240 241 retry -= 1; 242 } 243 244 /* Clear the configruation controller reset */ 245 val = ace_readw(0x18); 246 val &= ~0x0080; 247 ace_writew(val, 0x18); 248 249 /* Count the blocks we transfer this time. */ 250 start += trans; 251 blk_countdown -= trans; 252 } 253 254 release_cf_lock(); 255 256 return blkcnt; 257 } 258