1 /* 2 * Copyright (c) 2004 Picture Elements, Inc. 3 * Stephen Williams (XXXXXXXXXXXXXXXX) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * The Xilinx SystemACE chip support is activated by defining 10 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE 11 * to set the base address of the device. This code currently 12 * assumes that the chip is connected via a byte-wide bus. 13 * 14 * The CONFIG_SYSTEMACE also adds to fat support the device class 15 * "ace" that allows the user to execute "fatls ace 0" and the 16 * like. This works by making the systemace_get_dev function 17 * available to cmd_fat.c:get_dev and filling in a block device 18 * description that has all the bits needed for FAT support to 19 * read sectors. 20 * 21 * According to Xilinx technical support, before accessing the 22 * SystemACE CF you need to set the following control bits: 23 * FORCECFGMODE : 1 24 * CFGMODE : 0 25 * CFGSTART : 0 26 */ 27 28 #include <common.h> 29 #include <command.h> 30 #include <part.h> 31 #include <asm/io.h> 32 33 /* 34 * The ace_readw and writew functions read/write 16bit words, but the 35 * offset value is the BYTE offset as most used in the Xilinx 36 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined 37 * to be the base address for the chip, usually in the local 38 * peripheral bus. 39 */ 40 41 static u32 base = CONFIG_SYS_SYSTEMACE_BASE; 42 static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; 43 44 static void ace_writew(u16 val, unsigned off) 45 { 46 if (width == 8) { 47 #if !defined(__BIG_ENDIAN) 48 writeb(val >> 8, base + off); 49 writeb(val, base + off + 1); 50 #else 51 writeb(val, base + off); 52 writeb(val >> 8, base + off + 1); 53 #endif 54 } else 55 out16(base + off, val); 56 } 57 58 static u16 ace_readw(unsigned off) 59 { 60 if (width == 8) { 61 #if !defined(__BIG_ENDIAN) 62 return (readb(base + off) << 8) | readb(base + off + 1); 63 #else 64 return readb(base + off) | (readb(base + off + 1) << 8); 65 #endif 66 } 67 68 return in16(base + off); 69 } 70 71 static unsigned long systemace_read(struct blk_desc *block_dev, 72 unsigned long start, lbaint_t blkcnt, 73 void *buffer); 74 75 static struct blk_desc systemace_dev = { 0 }; 76 77 static int get_cf_lock(void) 78 { 79 int retry = 10; 80 81 /* CONTROLREG = LOCKREG */ 82 unsigned val = ace_readw(0x18); 83 val |= 0x0002; 84 ace_writew((val & 0xffff), 0x18); 85 86 /* Wait for MPULOCK in STATUSREG[15:0] */ 87 while (!(ace_readw(0x04) & 0x0002)) { 88 89 if (retry < 0) 90 return -1; 91 92 udelay(100000); 93 retry -= 1; 94 } 95 96 return 0; 97 } 98 99 static void release_cf_lock(void) 100 { 101 unsigned val = ace_readw(0x18); 102 val &= ~(0x0002); 103 ace_writew((val & 0xffff), 0x18); 104 } 105 106 static int systemace_get_dev(int dev, struct blk_desc **descp) 107 { 108 /* The first time through this, the systemace_dev object is 109 not yet initialized. In that case, fill it in. */ 110 if (systemace_dev.blksz == 0) { 111 systemace_dev.if_type = IF_TYPE_UNKNOWN; 112 systemace_dev.devnum = 0; 113 systemace_dev.part_type = PART_TYPE_UNKNOWN; 114 systemace_dev.type = DEV_TYPE_HARDDISK; 115 systemace_dev.blksz = 512; 116 systemace_dev.log2blksz = LOG2(systemace_dev.blksz); 117 systemace_dev.removable = 1; 118 systemace_dev.block_read = systemace_read; 119 120 /* 121 * Ensure the correct bus mode (8/16 bits) gets enabled 122 */ 123 ace_writew(width == 8 ? 0 : 0x0001, 0); 124 125 part_init(&systemace_dev); 126 127 } 128 *descp = &systemace_dev; 129 130 return 0; 131 } 132 133 /* 134 * This function is called (by dereferencing the block_read pointer in 135 * the dev_desc) to read blocks of data. The return value is the 136 * number of blocks read. A zero return indicates an error. 137 */ 138 static unsigned long systemace_read(struct blk_desc *block_dev, 139 unsigned long start, lbaint_t blkcnt, 140 void *buffer) 141 { 142 int retry; 143 unsigned blk_countdown; 144 unsigned char *dp = buffer; 145 unsigned val; 146 147 if (get_cf_lock() < 0) { 148 unsigned status = ace_readw(0x04); 149 150 /* If CFDETECT is false, card is missing. */ 151 if (!(status & 0x0010)) { 152 printf("** CompactFlash card not present. **\n"); 153 return 0; 154 } 155 156 printf("**** ACE locked away from me (STATUSREG=%04x)\n", 157 status); 158 return 0; 159 } 160 #ifdef DEBUG_SYSTEMACE 161 printf("... systemace read %lu sectors at %lu\n", blkcnt, start); 162 #endif 163 164 retry = 2000; 165 for (;;) { 166 val = ace_readw(0x04); 167 168 /* If CFDETECT is false, card is missing. */ 169 if (!(val & 0x0010)) { 170 printf("**** ACE CompactFlash not found.\n"); 171 release_cf_lock(); 172 return 0; 173 } 174 175 /* If RDYFORCMD, then we are ready to go. */ 176 if (val & 0x0100) 177 break; 178 179 if (retry < 0) { 180 printf("**** SystemACE not ready.\n"); 181 release_cf_lock(); 182 return 0; 183 } 184 185 udelay(1000); 186 retry -= 1; 187 } 188 189 /* The SystemACE can only transfer 256 sectors at a time, so 190 limit the current chunk of sectors. The blk_countdown 191 variable is the number of sectors left to transfer. */ 192 193 blk_countdown = blkcnt; 194 while (blk_countdown > 0) { 195 unsigned trans = blk_countdown; 196 197 if (trans > 256) 198 trans = 256; 199 200 #ifdef DEBUG_SYSTEMACE 201 printf("... transfer %lu sector in a chunk\n", trans); 202 #endif 203 /* Write LBA block address */ 204 ace_writew((start >> 0) & 0xffff, 0x10); 205 ace_writew((start >> 16) & 0x0fff, 0x12); 206 207 /* NOTE: in the Write Sector count below, a count of 0 208 causes a transfer of 256, so &0xff gives the right 209 value for whatever transfer count we want. */ 210 211 /* Write sector count | ReadMemCardData. */ 212 ace_writew((trans & 0xff) | 0x0300, 0x14); 213 214 /* 215 * For FPGA configuration via SystemACE is reset unacceptable 216 * CFGDONE bit in STATUSREG is not set to 1. 217 */ 218 #ifndef SYSTEMACE_CONFIG_FPGA 219 /* Reset the configruation controller */ 220 val = ace_readw(0x18); 221 val |= 0x0080; 222 ace_writew(val, 0x18); 223 #endif 224 225 retry = trans * 16; 226 while (retry > 0) { 227 int idx; 228 229 /* Wait for buffer to become ready. */ 230 while (!(ace_readw(0x04) & 0x0020)) { 231 udelay(100); 232 } 233 234 /* Read 16 words of 2bytes from the sector buffer. */ 235 for (idx = 0; idx < 16; idx += 1) { 236 unsigned short val = ace_readw(0x40); 237 *dp++ = val & 0xff; 238 *dp++ = (val >> 8) & 0xff; 239 } 240 241 retry -= 1; 242 } 243 244 /* Clear the configruation controller reset */ 245 val = ace_readw(0x18); 246 val &= ~0x0080; 247 ace_writew(val, 0x18); 248 249 /* Count the blocks we transfer this time. */ 250 start += trans; 251 blk_countdown -= trans; 252 } 253 254 release_cf_lock(); 255 256 return blkcnt; 257 } 258 259 U_BOOT_LEGACY_BLK(systemace) = { 260 .if_typename = "ace", 261 .if_type = IF_TYPE_SYSTEMACE, 262 .max_devs = 1, 263 .get_dev = systemace_get_dev, 264 }; 265