1 /* 2 * Copyright (c) 2004 Picture Elements, Inc. 3 * Stephen Williams (XXXXXXXXXXXXXXXX) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * The Xilinx SystemACE chip support is activated by defining 10 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE 11 * to set the base address of the device. This code currently 12 * assumes that the chip is connected via a byte-wide bus. 13 * 14 * The CONFIG_SYSTEMACE also adds to fat support the device class 15 * "ace" that allows the user to execute "fatls ace 0" and the 16 * like. This works by making the systemace_get_dev function 17 * available to cmd_fat.c:get_dev and filling in a block device 18 * description that has all the bits needed for FAT support to 19 * read sectors. 20 * 21 * According to Xilinx technical support, before accessing the 22 * SystemACE CF you need to set the following control bits: 23 * FORCECFGMODE : 1 24 * CFGMODE : 0 25 * CFGSTART : 0 26 */ 27 28 #include <common.h> 29 #include <command.h> 30 #include <part.h> 31 #include <asm/io.h> 32 33 /* 34 * The ace_readw and writew functions read/write 16bit words, but the 35 * offset value is the BYTE offset as most used in the Xilinx 36 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined 37 * to be the base address for the chip, usually in the local 38 * peripheral bus. 39 */ 40 41 static u32 base = CONFIG_SYS_SYSTEMACE_BASE; 42 static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; 43 44 static void ace_writew(u16 val, unsigned off) 45 { 46 if (width == 8) { 47 #if !defined(__BIG_ENDIAN) 48 writeb(val >> 8, base + off); 49 writeb(val, base + off + 1); 50 #else 51 writeb(val, base + off); 52 writeb(val >> 8, base + off + 1); 53 #endif 54 } else 55 out16(base + off, val); 56 } 57 58 static u16 ace_readw(unsigned off) 59 { 60 if (width == 8) { 61 #if !defined(__BIG_ENDIAN) 62 return (readb(base + off) << 8) | readb(base + off + 1); 63 #else 64 return readb(base + off) | (readb(base + off + 1) << 8); 65 #endif 66 } 67 68 return in16(base + off); 69 } 70 71 static struct blk_desc systemace_dev = { 0 }; 72 73 static int get_cf_lock(void) 74 { 75 int retry = 10; 76 77 /* CONTROLREG = LOCKREG */ 78 unsigned val = ace_readw(0x18); 79 val |= 0x0002; 80 ace_writew((val & 0xffff), 0x18); 81 82 /* Wait for MPULOCK in STATUSREG[15:0] */ 83 while (!(ace_readw(0x04) & 0x0002)) { 84 85 if (retry < 0) 86 return -1; 87 88 udelay(100000); 89 retry -= 1; 90 } 91 92 return 0; 93 } 94 95 static void release_cf_lock(void) 96 { 97 unsigned val = ace_readw(0x18); 98 val &= ~(0x0002); 99 ace_writew((val & 0xffff), 0x18); 100 } 101 102 /* 103 * This function is called (by dereferencing the block_read pointer in 104 * the dev_desc) to read blocks of data. The return value is the 105 * number of blocks read. A zero return indicates an error. 106 */ 107 static unsigned long systemace_read(struct blk_desc *block_dev, 108 unsigned long start, lbaint_t blkcnt, 109 void *buffer) 110 { 111 int retry; 112 unsigned blk_countdown; 113 unsigned char *dp = buffer; 114 unsigned val; 115 116 if (get_cf_lock() < 0) { 117 unsigned status = ace_readw(0x04); 118 119 /* If CFDETECT is false, card is missing. */ 120 if (!(status & 0x0010)) { 121 printf("** CompactFlash card not present. **\n"); 122 return 0; 123 } 124 125 printf("**** ACE locked away from me (STATUSREG=%04x)\n", 126 status); 127 return 0; 128 } 129 #ifdef DEBUG_SYSTEMACE 130 printf("... systemace read %lu sectors at %lu\n", blkcnt, start); 131 #endif 132 133 retry = 2000; 134 for (;;) { 135 val = ace_readw(0x04); 136 137 /* If CFDETECT is false, card is missing. */ 138 if (!(val & 0x0010)) { 139 printf("**** ACE CompactFlash not found.\n"); 140 release_cf_lock(); 141 return 0; 142 } 143 144 /* If RDYFORCMD, then we are ready to go. */ 145 if (val & 0x0100) 146 break; 147 148 if (retry < 0) { 149 printf("**** SystemACE not ready.\n"); 150 release_cf_lock(); 151 return 0; 152 } 153 154 udelay(1000); 155 retry -= 1; 156 } 157 158 /* The SystemACE can only transfer 256 sectors at a time, so 159 limit the current chunk of sectors. The blk_countdown 160 variable is the number of sectors left to transfer. */ 161 162 blk_countdown = blkcnt; 163 while (blk_countdown > 0) { 164 unsigned trans = blk_countdown; 165 166 if (trans > 256) 167 trans = 256; 168 169 #ifdef DEBUG_SYSTEMACE 170 printf("... transfer %lu sector in a chunk\n", trans); 171 #endif 172 /* Write LBA block address */ 173 ace_writew((start >> 0) & 0xffff, 0x10); 174 ace_writew((start >> 16) & 0x0fff, 0x12); 175 176 /* NOTE: in the Write Sector count below, a count of 0 177 causes a transfer of 256, so &0xff gives the right 178 value for whatever transfer count we want. */ 179 180 /* Write sector count | ReadMemCardData. */ 181 ace_writew((trans & 0xff) | 0x0300, 0x14); 182 183 /* 184 * For FPGA configuration via SystemACE is reset unacceptable 185 * CFGDONE bit in STATUSREG is not set to 1. 186 */ 187 #ifndef SYSTEMACE_CONFIG_FPGA 188 /* Reset the configruation controller */ 189 val = ace_readw(0x18); 190 val |= 0x0080; 191 ace_writew(val, 0x18); 192 #endif 193 194 retry = trans * 16; 195 while (retry > 0) { 196 int idx; 197 198 /* Wait for buffer to become ready. */ 199 while (!(ace_readw(0x04) & 0x0020)) { 200 udelay(100); 201 } 202 203 /* Read 16 words of 2bytes from the sector buffer. */ 204 for (idx = 0; idx < 16; idx += 1) { 205 unsigned short val = ace_readw(0x40); 206 *dp++ = val & 0xff; 207 *dp++ = (val >> 8) & 0xff; 208 } 209 210 retry -= 1; 211 } 212 213 /* Clear the configruation controller reset */ 214 val = ace_readw(0x18); 215 val &= ~0x0080; 216 ace_writew(val, 0x18); 217 218 /* Count the blocks we transfer this time. */ 219 start += trans; 220 blk_countdown -= trans; 221 } 222 223 release_cf_lock(); 224 225 return blkcnt; 226 } 227 228 static int systemace_get_dev(int dev, struct blk_desc **descp) 229 { 230 /* The first time through this, the systemace_dev object is 231 not yet initialized. In that case, fill it in. */ 232 if (systemace_dev.blksz == 0) { 233 systemace_dev.if_type = IF_TYPE_UNKNOWN; 234 systemace_dev.devnum = 0; 235 systemace_dev.part_type = PART_TYPE_UNKNOWN; 236 systemace_dev.type = DEV_TYPE_HARDDISK; 237 systemace_dev.blksz = 512; 238 systemace_dev.log2blksz = LOG2(systemace_dev.blksz); 239 systemace_dev.removable = 1; 240 systemace_dev.block_read = systemace_read; 241 242 /* 243 * Ensure the correct bus mode (8/16 bits) gets enabled 244 */ 245 ace_writew(width == 8 ? 0 : 0x0001, 0); 246 247 part_init(&systemace_dev); 248 } 249 *descp = &systemace_dev; 250 251 return 0; 252 } 253 254 U_BOOT_LEGACY_BLK(systemace) = { 255 .if_typename = "ace", 256 .if_type = IF_TYPE_SYSTEMACE, 257 .max_devs = 1, 258 .get_dev = systemace_get_dev, 259 }; 260