1 /* 2 * Copyright (c) 2004 Picture Elements, Inc. 3 * Stephen Williams (XXXXXXXXXXXXXXXX) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * The Xilinx SystemACE chip support is activated by defining 10 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE 11 * to set the base address of the device. This code currently 12 * assumes that the chip is connected via a byte-wide bus. 13 * 14 * The CONFIG_SYSTEMACE also adds to fat support the device class 15 * "ace" that allows the user to execute "fatls ace 0" and the 16 * like. This works by making the systemace_get_dev function 17 * available to cmd_fat.c:get_dev and filling in a block device 18 * description that has all the bits needed for FAT support to 19 * read sectors. 20 * 21 * According to Xilinx technical support, before accessing the 22 * SystemACE CF you need to set the following control bits: 23 * FORCECFGMODE : 1 24 * CFGMODE : 0 25 * CFGSTART : 0 26 */ 27 28 #include <common.h> 29 #include <command.h> 30 #include <systemace.h> 31 #include <part.h> 32 #include <asm/io.h> 33 34 /* 35 * The ace_readw and writew functions read/write 16bit words, but the 36 * offset value is the BYTE offset as most used in the Xilinx 37 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined 38 * to be the base address for the chip, usually in the local 39 * peripheral bus. 40 */ 41 42 static u32 base = CONFIG_SYS_SYSTEMACE_BASE; 43 static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; 44 45 static void ace_writew(u16 val, unsigned off) 46 { 47 if (width == 8) { 48 #if !defined(__BIG_ENDIAN) 49 writeb(val >> 8, base + off); 50 writeb(val, base + off + 1); 51 #else 52 writeb(val, base + off); 53 writeb(val >> 8, base + off + 1); 54 #endif 55 } else 56 out16(base + off, val); 57 } 58 59 static u16 ace_readw(unsigned off) 60 { 61 if (width == 8) { 62 #if !defined(__BIG_ENDIAN) 63 return (readb(base + off) << 8) | readb(base + off + 1); 64 #else 65 return readb(base + off) | (readb(base + off + 1) << 8); 66 #endif 67 } 68 69 return in16(base + off); 70 } 71 72 static unsigned long systemace_read(struct blk_desc *block_dev, 73 unsigned long start, lbaint_t blkcnt, 74 void *buffer); 75 76 static struct blk_desc systemace_dev = { 0 }; 77 78 static int get_cf_lock(void) 79 { 80 int retry = 10; 81 82 /* CONTROLREG = LOCKREG */ 83 unsigned val = ace_readw(0x18); 84 val |= 0x0002; 85 ace_writew((val & 0xffff), 0x18); 86 87 /* Wait for MPULOCK in STATUSREG[15:0] */ 88 while (!(ace_readw(0x04) & 0x0002)) { 89 90 if (retry < 0) 91 return -1; 92 93 udelay(100000); 94 retry -= 1; 95 } 96 97 return 0; 98 } 99 100 static void release_cf_lock(void) 101 { 102 unsigned val = ace_readw(0x18); 103 val &= ~(0x0002); 104 ace_writew((val & 0xffff), 0x18); 105 } 106 107 #ifdef CONFIG_PARTITIONS 108 struct blk_desc *systemace_get_dev(int dev) 109 { 110 /* The first time through this, the systemace_dev object is 111 not yet initialized. In that case, fill it in. */ 112 if (systemace_dev.blksz == 0) { 113 systemace_dev.if_type = IF_TYPE_UNKNOWN; 114 systemace_dev.devnum = 0; 115 systemace_dev.part_type = PART_TYPE_UNKNOWN; 116 systemace_dev.type = DEV_TYPE_HARDDISK; 117 systemace_dev.blksz = 512; 118 systemace_dev.log2blksz = LOG2(systemace_dev.blksz); 119 systemace_dev.removable = 1; 120 systemace_dev.block_read = systemace_read; 121 122 /* 123 * Ensure the correct bus mode (8/16 bits) gets enabled 124 */ 125 ace_writew(width == 8 ? 0 : 0x0001, 0); 126 127 part_init(&systemace_dev); 128 129 } 130 131 return &systemace_dev; 132 } 133 #endif 134 135 static int systemace_get_devp(int dev, struct blk_desc **descp) 136 { 137 *descp = systemace_get_dev(dev); 138 139 return 0; 140 } 141 142 /* 143 * This function is called (by dereferencing the block_read pointer in 144 * the dev_desc) to read blocks of data. The return value is the 145 * number of blocks read. A zero return indicates an error. 146 */ 147 static unsigned long systemace_read(struct blk_desc *block_dev, 148 unsigned long start, lbaint_t blkcnt, 149 void *buffer) 150 { 151 int retry; 152 unsigned blk_countdown; 153 unsigned char *dp = buffer; 154 unsigned val; 155 156 if (get_cf_lock() < 0) { 157 unsigned status = ace_readw(0x04); 158 159 /* If CFDETECT is false, card is missing. */ 160 if (!(status & 0x0010)) { 161 printf("** CompactFlash card not present. **\n"); 162 return 0; 163 } 164 165 printf("**** ACE locked away from me (STATUSREG=%04x)\n", 166 status); 167 return 0; 168 } 169 #ifdef DEBUG_SYSTEMACE 170 printf("... systemace read %lu sectors at %lu\n", blkcnt, start); 171 #endif 172 173 retry = 2000; 174 for (;;) { 175 val = ace_readw(0x04); 176 177 /* If CFDETECT is false, card is missing. */ 178 if (!(val & 0x0010)) { 179 printf("**** ACE CompactFlash not found.\n"); 180 release_cf_lock(); 181 return 0; 182 } 183 184 /* If RDYFORCMD, then we are ready to go. */ 185 if (val & 0x0100) 186 break; 187 188 if (retry < 0) { 189 printf("**** SystemACE not ready.\n"); 190 release_cf_lock(); 191 return 0; 192 } 193 194 udelay(1000); 195 retry -= 1; 196 } 197 198 /* The SystemACE can only transfer 256 sectors at a time, so 199 limit the current chunk of sectors. The blk_countdown 200 variable is the number of sectors left to transfer. */ 201 202 blk_countdown = blkcnt; 203 while (blk_countdown > 0) { 204 unsigned trans = blk_countdown; 205 206 if (trans > 256) 207 trans = 256; 208 209 #ifdef DEBUG_SYSTEMACE 210 printf("... transfer %lu sector in a chunk\n", trans); 211 #endif 212 /* Write LBA block address */ 213 ace_writew((start >> 0) & 0xffff, 0x10); 214 ace_writew((start >> 16) & 0x0fff, 0x12); 215 216 /* NOTE: in the Write Sector count below, a count of 0 217 causes a transfer of 256, so &0xff gives the right 218 value for whatever transfer count we want. */ 219 220 /* Write sector count | ReadMemCardData. */ 221 ace_writew((trans & 0xff) | 0x0300, 0x14); 222 223 /* 224 * For FPGA configuration via SystemACE is reset unacceptable 225 * CFGDONE bit in STATUSREG is not set to 1. 226 */ 227 #ifndef SYSTEMACE_CONFIG_FPGA 228 /* Reset the configruation controller */ 229 val = ace_readw(0x18); 230 val |= 0x0080; 231 ace_writew(val, 0x18); 232 #endif 233 234 retry = trans * 16; 235 while (retry > 0) { 236 int idx; 237 238 /* Wait for buffer to become ready. */ 239 while (!(ace_readw(0x04) & 0x0020)) { 240 udelay(100); 241 } 242 243 /* Read 16 words of 2bytes from the sector buffer. */ 244 for (idx = 0; idx < 16; idx += 1) { 245 unsigned short val = ace_readw(0x40); 246 *dp++ = val & 0xff; 247 *dp++ = (val >> 8) & 0xff; 248 } 249 250 retry -= 1; 251 } 252 253 /* Clear the configruation controller reset */ 254 val = ace_readw(0x18); 255 val &= ~0x0080; 256 ace_writew(val, 0x18); 257 258 /* Count the blocks we transfer this time. */ 259 start += trans; 260 blk_countdown -= trans; 261 } 262 263 release_cf_lock(); 264 265 return blkcnt; 266 } 267 268 U_BOOT_LEGACY_BLK(systemace) = { 269 .if_typename = "ace", 270 .if_type = IF_TYPE_SYSTEMACE, 271 .max_devs = 1, 272 .get_dev = systemace_get_devp, 273 }; 274