1 /* 2 * Copyright (c) 2004 Picture Elements, Inc. 3 * Stephen Williams (XXXXXXXXXXXXXXXX) 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * The Xilinx SystemACE chip support is activated by defining 10 * CONFIG_SYSTEMACE to turn on support, and CONFIG_SYS_SYSTEMACE_BASE 11 * to set the base address of the device. This code currently 12 * assumes that the chip is connected via a byte-wide bus. 13 * 14 * The CONFIG_SYSTEMACE also adds to fat support the device class 15 * "ace" that allows the user to execute "fatls ace 0" and the 16 * like. This works by making the systemace_get_dev function 17 * available to cmd_fat.c:get_dev and filling in a block device 18 * description that has all the bits needed for FAT support to 19 * read sectors. 20 * 21 * According to Xilinx technical support, before accessing the 22 * SystemACE CF you need to set the following control bits: 23 * FORCECFGMODE : 1 24 * CFGMODE : 0 25 * CFGSTART : 0 26 */ 27 28 #include <common.h> 29 #include <command.h> 30 #include <systemace.h> 31 #include <part.h> 32 #include <asm/io.h> 33 34 /* 35 * The ace_readw and writew functions read/write 16bit words, but the 36 * offset value is the BYTE offset as most used in the Xilinx 37 * datasheet for the SystemACE chip. The CONFIG_SYS_SYSTEMACE_BASE is defined 38 * to be the base address for the chip, usually in the local 39 * peripheral bus. 40 */ 41 42 static u32 base = CONFIG_SYS_SYSTEMACE_BASE; 43 static u32 width = CONFIG_SYS_SYSTEMACE_WIDTH; 44 45 static void ace_writew(u16 val, unsigned off) 46 { 47 if (width == 8) { 48 #if !defined(__BIG_ENDIAN) 49 writeb(val >> 8, base + off); 50 writeb(val, base + off + 1); 51 #else 52 writeb(val, base + off); 53 writeb(val >> 8, base + off + 1); 54 #endif 55 } else 56 out16(base + off, val); 57 } 58 59 static u16 ace_readw(unsigned off) 60 { 61 if (width == 8) { 62 #if !defined(__BIG_ENDIAN) 63 return (readb(base + off) << 8) | readb(base + off + 1); 64 #else 65 return readb(base + off) | (readb(base + off + 1) << 8); 66 #endif 67 } 68 69 return in16(base + off); 70 } 71 72 static unsigned long systemace_read(block_dev_desc_t *block_dev, 73 unsigned long start, lbaint_t blkcnt, 74 void *buffer); 75 76 static block_dev_desc_t systemace_dev = { 0 }; 77 78 static int get_cf_lock(void) 79 { 80 int retry = 10; 81 82 /* CONTROLREG = LOCKREG */ 83 unsigned val = ace_readw(0x18); 84 val |= 0x0002; 85 ace_writew((val & 0xffff), 0x18); 86 87 /* Wait for MPULOCK in STATUSREG[15:0] */ 88 while (!(ace_readw(0x04) & 0x0002)) { 89 90 if (retry < 0) 91 return -1; 92 93 udelay(100000); 94 retry -= 1; 95 } 96 97 return 0; 98 } 99 100 static void release_cf_lock(void) 101 { 102 unsigned val = ace_readw(0x18); 103 val &= ~(0x0002); 104 ace_writew((val & 0xffff), 0x18); 105 } 106 107 #ifdef CONFIG_PARTITIONS 108 block_dev_desc_t *systemace_get_dev(int dev) 109 { 110 /* The first time through this, the systemace_dev object is 111 not yet initialized. In that case, fill it in. */ 112 if (systemace_dev.blksz == 0) { 113 systemace_dev.if_type = IF_TYPE_UNKNOWN; 114 systemace_dev.dev = 0; 115 systemace_dev.part_type = PART_TYPE_UNKNOWN; 116 systemace_dev.type = DEV_TYPE_HARDDISK; 117 systemace_dev.blksz = 512; 118 systemace_dev.log2blksz = LOG2(systemace_dev.blksz); 119 systemace_dev.removable = 1; 120 systemace_dev.block_read = systemace_read; 121 122 /* 123 * Ensure the correct bus mode (8/16 bits) gets enabled 124 */ 125 ace_writew(width == 8 ? 0 : 0x0001, 0); 126 127 init_part(&systemace_dev); 128 129 } 130 131 return &systemace_dev; 132 } 133 #endif 134 135 /* 136 * This function is called (by dereferencing the block_read pointer in 137 * the dev_desc) to read blocks of data. The return value is the 138 * number of blocks read. A zero return indicates an error. 139 */ 140 static unsigned long systemace_read(block_dev_desc_t *block_dev, 141 unsigned long start, lbaint_t blkcnt, 142 void *buffer) 143 { 144 int retry; 145 unsigned blk_countdown; 146 unsigned char *dp = buffer; 147 unsigned val; 148 149 if (get_cf_lock() < 0) { 150 unsigned status = ace_readw(0x04); 151 152 /* If CFDETECT is false, card is missing. */ 153 if (!(status & 0x0010)) { 154 printf("** CompactFlash card not present. **\n"); 155 return 0; 156 } 157 158 printf("**** ACE locked away from me (STATUSREG=%04x)\n", 159 status); 160 return 0; 161 } 162 #ifdef DEBUG_SYSTEMACE 163 printf("... systemace read %lu sectors at %lu\n", blkcnt, start); 164 #endif 165 166 retry = 2000; 167 for (;;) { 168 val = ace_readw(0x04); 169 170 /* If CFDETECT is false, card is missing. */ 171 if (!(val & 0x0010)) { 172 printf("**** ACE CompactFlash not found.\n"); 173 release_cf_lock(); 174 return 0; 175 } 176 177 /* If RDYFORCMD, then we are ready to go. */ 178 if (val & 0x0100) 179 break; 180 181 if (retry < 0) { 182 printf("**** SystemACE not ready.\n"); 183 release_cf_lock(); 184 return 0; 185 } 186 187 udelay(1000); 188 retry -= 1; 189 } 190 191 /* The SystemACE can only transfer 256 sectors at a time, so 192 limit the current chunk of sectors. The blk_countdown 193 variable is the number of sectors left to transfer. */ 194 195 blk_countdown = blkcnt; 196 while (blk_countdown > 0) { 197 unsigned trans = blk_countdown; 198 199 if (trans > 256) 200 trans = 256; 201 202 #ifdef DEBUG_SYSTEMACE 203 printf("... transfer %lu sector in a chunk\n", trans); 204 #endif 205 /* Write LBA block address */ 206 ace_writew((start >> 0) & 0xffff, 0x10); 207 ace_writew((start >> 16) & 0x0fff, 0x12); 208 209 /* NOTE: in the Write Sector count below, a count of 0 210 causes a transfer of 256, so &0xff gives the right 211 value for whatever transfer count we want. */ 212 213 /* Write sector count | ReadMemCardData. */ 214 ace_writew((trans & 0xff) | 0x0300, 0x14); 215 216 /* 217 * For FPGA configuration via SystemACE is reset unacceptable 218 * CFGDONE bit in STATUSREG is not set to 1. 219 */ 220 #ifndef SYSTEMACE_CONFIG_FPGA 221 /* Reset the configruation controller */ 222 val = ace_readw(0x18); 223 val |= 0x0080; 224 ace_writew(val, 0x18); 225 #endif 226 227 retry = trans * 16; 228 while (retry > 0) { 229 int idx; 230 231 /* Wait for buffer to become ready. */ 232 while (!(ace_readw(0x04) & 0x0020)) { 233 udelay(100); 234 } 235 236 /* Read 16 words of 2bytes from the sector buffer. */ 237 for (idx = 0; idx < 16; idx += 1) { 238 unsigned short val = ace_readw(0x40); 239 *dp++ = val & 0xff; 240 *dp++ = (val >> 8) & 0xff; 241 } 242 243 retry -= 1; 244 } 245 246 /* Clear the configruation controller reset */ 247 val = ace_readw(0x18); 248 val &= ~0x0080; 249 ace_writew(val, 0x18); 250 251 /* Count the blocks we transfer this time. */ 252 start += trans; 253 blk_countdown -= trans; 254 } 255 256 release_cf_lock(); 257 258 return blkcnt; 259 } 260